[llvm] r312145 - [WebAssembly] Add target feature for atomics
Derek Schuff via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 30 11:07:45 PDT 2017
Author: dschuff
Date: Wed Aug 30 11:07:45 2017
New Revision: 312145
URL: http://llvm.org/viewvc/llvm-project?rev=312145&view=rev
Log:
[WebAssembly] Add target feature for atomics
Summary:
This tracks the WebAssembly threads feature proposal at
https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md
Differential Revision: https://reviews.llvm.org/D37300
Added:
llvm/trunk/test/CodeGen/WebAssembly/atomics.ll
Modified:
llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/trunk/lib/Target/WebAssembly/WebAssembly.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h
Modified: llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h Wed Aug 30 11:07:45 2017
@@ -128,6 +128,7 @@ inline unsigned GetDefaultP2Align(unsign
case WebAssembly::LOAD32_S_I64:
case WebAssembly::LOAD32_U_I64:
case WebAssembly::STORE32_I64:
+ case WebAssembly::ATOMIC_LOAD_I32:
return 2;
case WebAssembly::LOAD_I64:
case WebAssembly::LOAD_F64:
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssembly.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssembly.td?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssembly.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssembly.td Wed Aug 30 11:07:45 2017
@@ -25,6 +25,8 @@ include "llvm/Target/Target.td"
def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
"Enable 128-bit SIMD">;
+def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
+ "Enable Atomics">;
//===----------------------------------------------------------------------===//
// Architectures.
@@ -55,7 +57,8 @@ def : ProcessorModel<"mvp", NoSchedModel
def : ProcessorModel<"generic", NoSchedModel, []>;
// Latest and greatest experimental version of WebAssembly. Bugs included!
-def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
+def : ProcessorModel<"bleeding-edge", NoSchedModel,
+ [FeatureSIMD128, FeatureAtomics]>;
//===----------------------------------------------------------------------===//
// Target Declaration
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Wed Aug 30 11:07:45 2017
@@ -146,6 +146,8 @@ WebAssemblyTargetLowering::WebAssemblyTa
// Trap lowers to wasm unreachable
setOperationAction(ISD::TRAP, MVT::Other, Legal);
+
+ setMaxAtomicSizeInBitsSupported(64);
}
FastISel *WebAssemblyTargetLowering::createFastISel(
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td Wed Aug 30 11:07:45 2017
@@ -12,19 +12,23 @@
///
//===----------------------------------------------------------------------===//
-// TODO: Implement atomic instructions.
-
-//===----------------------------------------------------------------------===//
-// Atomic fences
-//===----------------------------------------------------------------------===//
-
-// TODO: add atomic fences here...
-
//===----------------------------------------------------------------------===//
// Atomic loads
//===----------------------------------------------------------------------===//
-// TODO: add atomic loads here...
+let Defs = [ARGUMENTS] in {
+// TODO: add the rest of the atomic loads
+// TODO: factor out 0xfe atomic prefix?
+def ATOMIC_LOAD_I32 : ATOMIC_I<(outs I32:$dst),
+ (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
+ [], "i32.atomic.load\t$dst, ${off}(${addr})${p2align}",
+ 0xfe10>;
+} // Defs = [ARGUMENTS]
+
+// Select loads with no constant offset.
+let Predicates = [HasAtomics] in {
+def : Pat<(i32 (atomic_load I32:$addr)), (ATOMIC_LOAD_I32 0, 0, $addr)>;
+}
//===----------------------------------------------------------------------===//
// Atomic stores
@@ -45,3 +49,4 @@
// Store-release-exclusives.
// And clear exclusive.
+
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td Wed Aug 30 11:07:45 2017
@@ -32,6 +32,10 @@ class SIMD_I<dag oops, dag iops, list<da
string asmstr = "", bits<32> inst = -1>
: I<oops, iops, pattern, asmstr, inst>, Requires<[HasSIMD128]>;
+class ATOMIC_I<dag oops, dag iops, list<dag> pattern,
+ string asmstr = "", bits<32> inst = -1>
+ : I<oops, iops, pattern, asmstr, inst>, Requires<[HasAtomics]>;
+
// Unary and binary instructions, for the local types that WebAssembly supports.
multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst, bits<32> i64Inst> {
def _I32 : I<(outs I32:$dst), (ins I32:$src),
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td Wed Aug 30 11:07:45 2017
@@ -20,6 +20,8 @@ def HasAddr32 : Predicate<"!Subtarget->h
def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
AssemblerPredicate<"FeatureSIMD128", "simd128">;
+def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
+ AssemblerPredicate<"FeatureAtomics", "atomics">;
//===----------------------------------------------------------------------===//
// WebAssembly-specific DAG Node Types.
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp Wed Aug 30 11:07:45 2017
@@ -96,6 +96,7 @@ bool WebAssemblySetP2AlignOperands::runO
case WebAssembly::LOAD16_U_I64:
case WebAssembly::LOAD32_S_I64:
case WebAssembly::LOAD32_U_I64:
+ case WebAssembly::ATOMIC_LOAD_I32:
RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo);
break;
case WebAssembly::STORE_I32:
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp Wed Aug 30 11:07:45 2017
@@ -41,7 +41,7 @@ WebAssemblySubtarget::WebAssemblySubtarg
const std::string &FS,
const TargetMachine &TM)
: WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
- CPUString(CPU), TargetTriple(TT), FrameLowering(),
+ HasAtomics(false), CPUString(CPU), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
TLInfo(TM, *this) {}
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h?rev=312145&r1=312144&r2=312145&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h Wed Aug 30 11:07:45 2017
@@ -30,6 +30,7 @@ namespace llvm {
class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
bool HasSIMD128;
+ bool HasAtomics;
/// String name of used CPU.
std::string CPUString;
@@ -74,6 +75,7 @@ public:
// Predicates used by WebAssemblyInstrInfo.td.
bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
bool hasSIMD128() const { return HasSIMD128; }
+ bool hasAtomics() const { return HasAtomics; }
/// Parses features string setting specified subtarget options. Definition of
/// function is auto generated by tblgen.
Added: llvm/trunk/test/CodeGen/WebAssembly/atomics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/atomics.ll?rev=312145&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/atomics.ll (added)
+++ llvm/trunk/test/CodeGen/WebAssembly/atomics.ll Wed Aug 30 11:07:45 2017
@@ -0,0 +1,19 @@
+; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=+atomics | FileCheck %s
+
+; Test that atomic loads are assembled properly.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown-wasm"
+
+; CHECK-LABEL: load_i32_atomic:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
+; CHECK-NEXT: i32.atomic.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
+; CHECK-NEXT: return $pop[[NUM]]{{$}}
+
+define i32 @load_i32_atomic(i32 *%p) {
+ %v = load atomic i32, i32* %p seq_cst, align 4
+ ret i32 %v
+}
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