[PATCH] D23566: [RISCV 8/10] Add support for all RV32I instructions

[Ana Pazos via Phabricator via llvm-commits]

apazos added inline comments.


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Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:272
+        case 'w': Imm |= RISCVFenceField::W; break;
+        default: llvm_unreachable("FenceArg must contain only [iorw]");
+      }
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Another code standard note: be consistent where you put the default case, people usually put it as the first case to avoid forgetting it.


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Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:452
+    // Parse memory base register if present
+    if (getLexer().getKind() == AsmToken::LParen) {
+      return parseMemOpBaseReg(Operands) != MatchOperand_Success;
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code standard reminder: {} are unnecessary with one line statement.


https://reviews.llvm.org/D23566