[PATCH] D36936: [InstCombine] Consider more cases where SimplifyDemandedUseBits do not converting AShr to LShr

[Amjad Aboud via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311773: [InstCombine] Consider more cases where SimplifyDemandedUseBits does not… (authored by aaboud).

Changed prior to commit:
  https://reviews.llvm.org/D36936?vs=111947&id=112676#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36936

Files:
  llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/trunk/test/Transforms/InstCombine/trunc.ll


Index: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
===================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -521,9 +521,12 @@
       if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
         return I;
 
+      unsigned SignBits = ComputeNumSignBits(I->getOperand(0), Depth + 1, CxtI);
+
       assert(!Known.hasConflict() && "Bits known to be one AND zero?");
-      // Compute the new bits that are at the top now.
-      APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
+      // Compute the new bits that are at the top now plus sign bits.
+      APInt HighBits(APInt::getHighBitsSet(
+          BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
       Known.Zero.lshrInPlace(ShiftAmt);
       Known.One.lshrInPlace(ShiftAmt);
 
Index: llvm/trunk/test/Transforms/InstCombine/trunc.ll
===================================================================
--- llvm/trunk/test/Transforms/InstCombine/trunc.ll
+++ llvm/trunk/test/Transforms/InstCombine/trunc.ll
@@ -89,6 +89,23 @@
   ret i32 %D
 }
 
+; Test case where 'ashr' demanded bits does not contain any of the high bits,
+; but does contain sign bits, where the sign bit is not known to be zero.
+define i16 @ashr_mul_sign_bits(i8 %X, i8 %Y) {
+; CHECK-LABEL: @ashr_mul_sign_bits(
+; CHECK-NEXT:    [[A:%.*]] = sext i8 %X to i16
+; CHECK-NEXT:    [[B:%.*]] = sext i8 %Y to i16
+; CHECK-NEXT:    [[C:%.*]] = mul nsw i16 [[A]], [[B]]
+; CHECK-NEXT:    [[D:%.*]] = ashr i16 [[C]], 3
+; CHECK-NEXT:    ret i16 [[D]]
+  %A = sext i8 %X to i32
+  %B = sext i8 %Y to i32
+  %C = mul i32 %A, %B
+  %D = ashr i32 %C, 3
+  %E = trunc i32 %D to i16
+  ret i16 %E
+}
+
 define i16 @ashr_mul(i8 %X, i8 %Y) {
 ; CHECK-LABEL: @ashr_mul(
 ; CHECK-NEXT:    [[A:%.*]] = sext i8 %X to i16


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