[llvm] r311747 - [X86] Add TBM instructions to X86InstrInfo::isDefConvertible.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 18:59:06 PDT 2017
Author: ctopper
Date: Thu Aug 24 18:59:06 2017
New Revision: 311747
URL: http://llvm.org/viewvc/llvm-project?rev=311747&view=rev
Log:
[X86] Add TBM instructions to X86InstrInfo::isDefConvertible.
This allows us to remove "test" instructions and use the flags from the TBM instructions directly.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=311747&r1=311746&r2=311747&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Aug 24 18:59:06 2017
@@ -7148,6 +7148,22 @@ inline static bool isDefConvertible(Mach
case X86::TZCNT16rr: case X86::TZCNT16rm:
case X86::TZCNT32rr: case X86::TZCNT32rm:
case X86::TZCNT64rr: case X86::TZCNT64rm:
+ case X86::BEXTRI32ri: case X86::BEXTRI32mi:
+ case X86::BEXTRI64ri: case X86::BEXTRI64mi:
+ case X86::BLCFILL32rr: case X86::BLCFILL32rm:
+ case X86::BLCFILL64rr: case X86::BLCFILL64rm:
+ case X86::BLCI32rr: case X86::BLCI32rm:
+ case X86::BLCI64rr: case X86::BLCI64rm:
+ case X86::BLCIC32rr: case X86::BLCIC32rm:
+ case X86::BLCIC64rr: case X86::BLCIC64rm:
+ case X86::BLCMSK32rr: case X86::BLCMSK32rm:
+ case X86::BLCMSK64rr: case X86::BLCMSK64rm:
+ case X86::BLCS32rr: case X86::BLCS32rm:
+ case X86::BLCS64rr: case X86::BLCS64rm:
+ case X86::BLSFILL32rr: case X86::BLSFILL32rm:
+ case X86::BLSFILL64rr: case X86::BLSFILL64rm:
+ case X86::BLSIC32rr: case X86::BLSIC32rm:
+ case X86::BLSIC64rr: case X86::BLSIC64rm:
return true;
}
}
Modified: llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll?rev=311747&r1=311746&r2=311747&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm-intrinsics-x86_64.ll Thu Aug 24 18:59:06 2017
@@ -28,7 +28,6 @@ define i32 @test_x86_tbm_bextri_u32_z(i3
; CHECK-LABEL: test_x86_tbm_bextri_u32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, %edi, %eax # imm = 0xAFE
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
entry:
@@ -65,7 +64,6 @@ define i64 @test_x86_tbm_bextri_u64_z(i6
; CHECK-LABEL: test_x86_tbm_bextri_u64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: bextr $2814, %rdi, %rax # imm = 0xAFE
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=311747&r1=311746&r2=311747&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm_patterns.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm_patterns.ll Thu Aug 24 18:59:06 2017
@@ -28,7 +28,6 @@ define i32 @test_x86_tbm_bextri_u32_z(i3
; CHECK-LABEL: test_x86_tbm_bextri_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = lshr i32 %a, 4
@@ -63,9 +62,7 @@ define i64 @test_x86_tbm_bextri_u64_z(i6
; CHECK-LABEL: test_x86_tbm_bextri_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
-; CHECK-NEXT: testl %eax, %eax
-; CHECK-NEXT: cmovneq %rax, %rsi
-; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = lshr i64 %a, 4
%t1 = and i64 %t0, 4095
@@ -88,7 +85,6 @@ define i32 @test_x86_tbm_blcfill_u32_z(i
; CHECK-LABEL: test_x86_tbm_blcfill_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcfill %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
@@ -112,7 +108,6 @@ define i64 @test_x86_tbm_blcfill_u64_z(i
; CHECK-LABEL: test_x86_tbm_blcfill_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcfill %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
@@ -137,7 +132,6 @@ define i32 @test_x86_tbm_blci_u32_z(i32
; CHECK-LABEL: test_x86_tbm_blci_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blci %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 1, %a
@@ -163,7 +157,6 @@ define i64 @test_x86_tbm_blci_u64_z(i64
; CHECK-LABEL: test_x86_tbm_blci_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blci %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 1, %a
@@ -209,7 +202,6 @@ define i32 @test_x86_tbm_blcic_u32_z(i32
; CHECK-LABEL: test_x86_tbm_blcic_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcic %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
@@ -235,7 +227,6 @@ define i64 @test_x86_tbm_blcic_u64_z(i64
; CHECK-LABEL: test_x86_tbm_blcic_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcic %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
@@ -260,7 +251,6 @@ define i32 @test_x86_tbm_blcmsk_u32_z(i3
; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcmsk %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
@@ -284,7 +274,6 @@ define i64 @test_x86_tbm_blcmsk_u64_z(i6
; CHECK-LABEL: test_x86_tbm_blcmsk_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcmsk %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
@@ -308,7 +297,6 @@ define i32 @test_x86_tbm_blcs_u32_z(i32
; CHECK-LABEL: test_x86_tbm_blcs_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcs %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, 1
@@ -332,7 +320,6 @@ define i64 @test_x86_tbm_blcs_u64_z(i64
; CHECK-LABEL: test_x86_tbm_blcs_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blcs %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, 1
@@ -356,7 +343,6 @@ define i32 @test_x86_tbm_blsfill_u32_z(i
; CHECK-LABEL: test_x86_tbm_blsfill_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blsfill %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = add i32 %a, -1
@@ -380,7 +366,6 @@ define i64 @test_x86_tbm_blsfill_u64_z(i
; CHECK-LABEL: test_x86_tbm_blsfill_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blsfill %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = add i64 %a, -1
@@ -405,7 +390,6 @@ define i32 @test_x86_tbm_blsic_u32_z(i32
; CHECK-LABEL: test_x86_tbm_blsic_u32_z:
; CHECK: # BB#0:
; CHECK-NEXT: blsic %edi, %eax
-; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: retq
%t0 = xor i32 %a, -1
@@ -431,7 +415,6 @@ define i64 @test_x86_tbm_blsic_u64_z(i64
; CHECK-LABEL: test_x86_tbm_blsic_u64_z:
; CHECK: # BB#0:
; CHECK-NEXT: blsic %rdi, %rax
-; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: retq
%t0 = xor i64 %a, -1
More information about the llvm-commits
mailing list