[PATCH] D37069: [x86] use the IR type of formal args to create assertzext/assertsext and scalar truncate nodes

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:3009
         // Handle MMX values passed in XMM regs.
-        if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
+        if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1) {
           ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
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aaboud wrote:
> by the way, do we need these parentheses here and below with the one line "else if"/"else" ?
Technically, no - but since one clause in this chain had them (and I thought that has a good thing for readability), then all clauses in this chain should have them for symmetry. I think the LLVM coding guidelines are purposely ambiguous on this, but my preference is to brace more. It improves readability and helps avoid bugs if someone comes along and wants to add more code or comments - which I probably should do if this patch is functionally correct and going to proceed :)


https://reviews.llvm.org/D37069