[PATCH] D37102: [AArch64] Add FMOVH0: materialize 0 using zero register for f16 values

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

Instead of loading 0 from a constant pool, it's of course much better to materialize it using an fmov and the zero register.

      

Thanks to Ahmed Bougacha for the suggestion.


https://reviews.llvm.org/D37102

Files:
  lib/Target/AArch64/AArch64AsmPrinter.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/f16-imm.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D37102.112531.patch
Type: text/x-patch
Size: 4565 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170824/5c2fe66b/attachment.bin>