[PATCH] D34160: [Power9] Exploit vinserth instruction

Graham Yiu via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 23 10:35:35 PDT 2017


gyiu added inline comments.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7903
+    // undef.
+    if (V2.isUndef()) {
+      ShiftElts = 0;
----------------
nemanjai wrote:
> You should be able to get rid of this condition here.
> - Move the assignment `if (V.isUndef()) V2 = V1;` above here
> - Use the `OriginalOrderLow` if the two vectors are the same
> 
> The rest should fall out naturally and we'll do the shift for the single-input case as well. And the code will also be simpler.
@nemanjai I created Issue #410 on github to address the issue when using vector shifts in the case when both inputs are the same vector.  There's further investigation that's required as it's not clear which input/output registers the (vector shift + vector extract) sequence uses in this case.  I would rather do this change as part of that work item instead.


Repository:
  rL LLVM

https://reviews.llvm.org/D34160





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