[PATCH] D37051: Model cache size and associativity in TargetTransformInfo

[Roman Lebedev via llvm-commits]

On Wed, Aug 23, 2017 at 1:55 PM, Alex Bradbury via Phabricator via
llvm-commits <llvm-commits at lists.llvm.org> wrote:
> asb added inline comments.
>
>
> ================
> Comment at: include/llvm/Analysis/TargetTransformInfoImpl.h:343
>
> +  unsigned getCacheSize(TargetTransformInfo::CacheLevel Level) {
> +    switch (Level) {
> ----------------
> fhahn wrote:
>> Maybe it would be safer to be conservative and return 0 here, similar to what getCacheLineSize does currently? That allows passes to check if the target provides accurate information ( != 0).
>>
>> For example, for ARM Cortex cores the level 1 cache size can vary between 0KByte and 64KByte. [1], [2]
>>
>> Also, we already have getCacheLineSize. Would it make sense to express the cache size in terms of cache lines, (eg X * Cache line size)? That would make it slightly easier to keep them in sync and avoid situations where getCacheSize() is not a multiple of getCacheLineSize()
>>
>>
>> [1] https://en.wikipedia.org/wiki/Comparison_of_ARMv8-A_cores
>> [2] https://en.wikipedia.org/wiki/ARM_Cortex-M
> I wondered about returning 0 too, but also think we need a new sentinel value. This function should be able to indicate 1) cache is known size X, 2) cache is unknown size, 3) cache is known size 0 (e.g. there is no L2).
llvm::Optional<int> ?
unknown size - optional is uninitialized
0 size - optional is initialized to 0
X size - optional is initialized to X

> https://reviews.llvm.org/D37051
>
>
>
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