[PATCH] D36890: [X86] Emit testl instead of testb for select condition where possible

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

I haven't looked at AssertZext before, so I'm going to learn something today. :)
I'm curious about this sequence:

        t4: i32 = AssertZext t2, ValueType:ch:i8
      t5: i8 = truncate t4
    t7: i8 = AssertZext t5, ValueType:ch:i1
  t8: i1 = truncate t7

1. If an AssertZext (t7) has a truncate (t5) source operand with no other uses, can we reverse those ops (effectively, we make the assert stronger)?
2. This leads to another question: if an AssertZext is preceded by a weaker AssertZext, can we eliminate the weaker AssertZext?

FWIW, I drafted #1, and it solves this bug (we get the 32-bit ops you're getting here). It also creates several other diffs. At first glance, they look like x86 improvements to me, but I could use a 2nd opinion on that. 
If that's a reasonable generic DAG transform, I'd prefer to do that rather than complicating the x86-specific code even more.


https://reviews.llvm.org/D36890