[llvm] r311061 - ARM: mark CPSR as clobbered for Windows VLAs

[Saleem Abdulrasool via llvm-commits]

Indeed I did :-).  It is very targeted and trivial and I believe it to be a
very low-risk fix for a nasty codegen issue.

On Mon, Aug 21, 2017 at 4:57 PM, Hans Wennborg <hans at chromium.org> wrote:

> I think you asked on IRC for this to be merged?
>
> On Wed, Aug 16, 2017 at 7:42 PM, Saleem Abdulrasool via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
> > Author: compnerd
> > Date: Wed Aug 16 19:42:24 2017
> > New Revision: 311061
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=311061&view=rev
> > Log:
> > ARM: mark CPSR as clobbered for Windows VLAs
> >
> > When lowering a VLA, we emit a __chstk call.  However, this call can
> > internally clobber CPSR.  We did not mark this register as an ImpDef,
> > which could potentially allow a comparison to be hoisted above the call
> > to `__chkstk`.  In such a case, the CPSR could be clobbered, and the
> > check invalidated.  When the support was initially added, it seemed that
> > the call would take care of preventing CPSR from being clobbered, but
> > this is not the case.  Mark the register as clobbered to fix a possible
> > state corruption.
> >
> > Added:
> >     llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll
> > Modified:
> >     llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> ARM/ARMISelLowering.cpp?rev=311061&r1=311060&r2=311061&view=diff
> > ============================================================
> ==================
> > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug 16 19:42:24
> 2017
> > @@ -8790,6 +8790,8 @@ ARMTargetLowering::EmitLowered__chkstk(M
> >          .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
> >          .addReg(ARM::R4, RegState::Implicit | RegState::Define)
> >          .addReg(ARM::R12,
> > +                RegState::Implicit | RegState::Define | RegState::Dead)
> > +        .addReg(ARM::CPSR,
> >                  RegState::Implicit | RegState::Define | RegState::Dead);
> >      break;
> >    case CodeModel::Large: {
> > @@ -8804,6 +8806,8 @@ ARMTargetLowering::EmitLowered__chkstk(M
> >          .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
> >          .addReg(ARM::R4, RegState::Implicit | RegState::Define)
> >          .addReg(ARM::R12,
> > +                RegState::Implicit | RegState::Define | RegState::Dead)
> > +        .addReg(ARM::CPSR,
> >                  RegState::Implicit | RegState::Define | RegState::Dead);
> >      break;
> >    }
> >
> > Added: llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/ARM/Windows/vla-cpsr.ll?rev=311061&view=auto
> > ============================================================
> ==================
> > --- llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll (added)
> > +++ llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll Wed Aug 16 19:42:24
> 2017
> > @@ -0,0 +1,13 @@
> > +; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null
> %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
> > +
> > +declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
> > +
> > +define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
> > +entry:
> > +  %vla = alloca i8, i32 %i, align 1
> > +  call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
> > +  ret void
> > +}
> > +
> > +; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def>,
> %SP<imp-use>, %R4<imp-use,kill>, %R4<imp-def>, %R12<imp-def,dead>,
> %CPSR<imp-def,dead>
> > +
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>



-- 
Saleem Abdulrasool
compnerd (at) compnerd (dot) org
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