[PATCH] D36795: [SystemZ] Increase number of LOCRs emitted by passing regalloc hints

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand added a comment.

In https://reviews.llvm.org/D36795#845610, @jonpa wrote:

> I think that to handle those cases we would have to constrain regclasses somehow after coalescing.


This could be done in TRI->updateRegAllocHint, possibly?

> And maybe better than giving hard hints would be to immediately after one out of two GRX32 regs gets allocated constrain the other virtreg.

Not sure if there is currently any place where this can be done.  Does the register allocator (all of them) even go through registers one-by-one and assigns them, or is the algorithm more complex?

> I am not convinced still that making this guarantee generally is possible (without a target pre-ra pass to do this), especially not for all different kind of register allocators that are around / may appear. It seems that some kind of broader construct is needed in order to always be sure this never goes wrong. Maybe a property of a register class somehow that all operands of any MI must belong to one out of two sub regclasses...? :-/

Note that this, while appropriate for LOCRMux, would be too restrictive for certain other operations.  For example, for comparisons, we can allow high-high, low-low, and also high-low compares, but not low-high compares, and similarly for add and subtract.  (For comparison, the alternatives / constraints mechanism in GCC allows targets to exactly describe the valid combinations for each instruction, and the register allocator will chose any of those as appropriate.)


https://reviews.llvm.org/D36795