[llvm] r311316 - [ARM][AArch64] Cortex-A75 and Cortex-A55 support
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 21 01:43:06 PDT 2017
Author: sam_parker
Date: Mon Aug 21 01:43:06 2017
New Revision: 311316
URL: http://llvm.org/viewvc/llvm-project?rev=311316&view=rev
Log:
[ARM][AArch64] Cortex-A75 and Cortex-A55 support
This patch introduces support for Cortex-A75 and Cortex-A55, Arm's
latest big.LITTLE A-class cores. They implement the ARMv8.2-A
architecture, including the cryptography and RAS extensions, plus
the optional dot product extension. They also implement the RCpc
AArch64 extension from ARMv8.3-A.
Cortex-A75:
https://developer.arm.com/products/processors/cortex-a/cortex-a75
Cortex-A55:
https://developer.arm.com/products/processors/cortex-a/cortex-a55
Differential Revision: https://reviews.llvm.org/D36667
Modified:
llvm/trunk/include/llvm/Support/AArch64TargetParser.def
llvm/trunk/include/llvm/Support/ARMTargetParser.def
llvm/trunk/include/llvm/Support/TargetParser.h
llvm/trunk/lib/Support/TargetParser.cpp
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/test/CodeGen/AArch64/cpus.ll
llvm/trunk/test/CodeGen/AArch64/remat.ll
llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s
llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s
llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s
llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt
llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
llvm/trunk/unittests/Support/TargetParserTest.cpp
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Mon Aug 21 01:43:06 2017
@@ -32,7 +32,8 @@ AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2
AARCH64_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
- AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
+ AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_RCPC))
#undef AARCH64_ARCH
#ifndef AARCH64_ARCH_EXT_NAME
@@ -51,6 +52,7 @@ AARCH64_ARCH_EXT_NAME("fp16", AArch6
AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
+AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
@@ -60,12 +62,16 @@ AARCH64_CPU_NAME("cortex-a35", ARMV8A, F
(AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,
(AArch64::AEK_CRC))
+AARCH64_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC))
AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))
AARCH64_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_CRC))
+AARCH64_CPU_NAME("cortex-a75", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC))
AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_NONE))
AARCH64_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Mon Aug 21 01:43:06 2017
@@ -130,6 +130,7 @@ ARM_ARCH_EXT_NAME("invalid", ARM::AEK_I
ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr)
ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc")
ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto")
+ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod","-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr)
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), nullptr, nullptr)
@@ -241,9 +242,13 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainlin
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
+ARM_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a72", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a73", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
+ARM_CPU_NAME("cortex-a75", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m1", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
ARM_CPU_NAME("exynos-m2", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
Modified: llvm/trunk/include/llvm/Support/TargetParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetParser.h (original)
+++ llvm/trunk/include/llvm/Support/TargetParser.h Mon Aug 21 01:43:06 2017
@@ -70,21 +70,22 @@ enum class ArchKind {
// Arch extension modifiers for CPUs.
enum ArchExtKind : unsigned {
- AEK_INVALID = 0x0,
- AEK_NONE = 0x1,
- AEK_CRC = 0x2,
- AEK_CRYPTO = 0x4,
- AEK_FP = 0x8,
- AEK_HWDIVTHUMB = 0x10,
- AEK_HWDIVARM = 0x20,
- AEK_MP = 0x40,
- AEK_SIMD = 0x80,
- AEK_SEC = 0x100,
- AEK_VIRT = 0x200,
- AEK_DSP = 0x400,
- AEK_FP16 = 0x800,
- AEK_RAS = 0x1000,
- AEK_SVE = 0x2000,
+ AEK_INVALID = 0,
+ AEK_NONE = 1,
+ AEK_CRC = 1 << 1,
+ AEK_CRYPTO = 1 << 2,
+ AEK_FP = 1 << 3,
+ AEK_HWDIVTHUMB = 1 << 4,
+ AEK_HWDIVARM = 1 << 5,
+ AEK_MP = 1 << 6,
+ AEK_SIMD = 1 << 7,
+ AEK_SEC = 1 << 8,
+ AEK_VIRT = 1 << 9,
+ AEK_DSP = 1 << 10,
+ AEK_FP16 = 1 << 11,
+ AEK_RAS = 1 << 12,
+ AEK_SVE = 1 << 13,
+ AEK_DOTPROD = 1 << 14,
// Unsupported extensions.
AEK_OS = 0x8000000,
AEK_IWMMXT = 0x10000000,
@@ -156,18 +157,19 @@ enum class ArchKind {
// Arch extension modifiers for CPUs.
enum ArchExtKind : unsigned {
- AEK_INVALID = 0x0,
- AEK_NONE = 0x1,
- AEK_CRC = 0x2,
- AEK_CRYPTO = 0x4,
- AEK_FP = 0x8,
- AEK_SIMD = 0x10,
- AEK_FP16 = 0x20,
- AEK_PROFILE = 0x40,
- AEK_RAS = 0x80,
- AEK_LSE = 0x100,
- AEK_SVE = 0x200,
- AEK_DOTPROD = 0x400
+ AEK_INVALID = 0,
+ AEK_NONE = 1,
+ AEK_CRC = 1 << 1,
+ AEK_CRYPTO = 1 << 2,
+ AEK_FP = 1 << 3,
+ AEK_SIMD = 1 << 4,
+ AEK_FP16 = 1 << 5,
+ AEK_PROFILE = 1 << 6,
+ AEK_RAS = 1 << 7,
+ AEK_LSE = 1 << 8,
+ AEK_SVE = 1 << 9,
+ AEK_DOTPROD = 1 << 10,
+ AEK_RCPC = 1 << 11
};
StringRef getCanonicalArchName(StringRef Arch);
Modified: llvm/trunk/lib/Support/TargetParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Support/TargetParser.cpp (original)
+++ llvm/trunk/lib/Support/TargetParser.cpp Mon Aug 21 01:43:06 2017
@@ -235,6 +235,16 @@ bool llvm::ARM::getExtensionFeatures(uns
else
Features.push_back("-dsp");
+ if (Extensions & ARM::AEK_RAS)
+ Features.push_back("+ras");
+ else
+ Features.push_back("-ras");
+
+ if (Extensions & ARM::AEK_DOTPROD)
+ Features.push_back("+dotprod");
+ else
+ Features.push_back("-dotprod");
+
return getHWDivFeatures(Extensions, Features);
}
@@ -438,6 +448,8 @@ bool llvm::AArch64::getExtensionFeatures
Features.push_back("+crc");
if (Extensions & AArch64::AEK_CRYPTO)
Features.push_back("+crypto");
+ if (Extensions & AArch64::AEK_DOTPROD)
+ Features.push_back("+dotprod");
if (Extensions & AArch64::AEK_FP16)
Features.push_back("+fullfp16");
if (Extensions & AArch64::AEK_PROFILE)
@@ -448,6 +460,8 @@ bool llvm::AArch64::getExtensionFeatures
Features.push_back("+lse");
if (Extensions & AArch64::AEK_SVE)
Features.push_back("+sve");
+ if (Extensions & AArch64::AEK_RCPC)
+ Features.push_back("+rcpc");
return true;
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Mon Aug 21 01:43:06 2017
@@ -210,6 +210,18 @@ def ProcA53 : SubtargetFeature<"a53"
FeatureUseAA
]>;
+def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
+ "Cortex-A55 ARM processors", [
+ FeatureCrypto,
+ FeatureFPARMv8,
+ FeatureFuseAES,
+ FeatureNEON,
+ FeatureFullFP16,
+ FeatureDotProd,
+ FeatureRCPC,
+ FeaturePerfMon
+ ]>;
+
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,
@@ -245,6 +257,18 @@ def ProcA73 : SubtargetFeature<"a73"
FeaturePerfMon
]>;
+def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
+ "Cortex-A75 ARM processors", [
+ FeatureCrypto,
+ FeatureFPARMv8,
+ FeatureFuseAES,
+ FeatureNEON,
+ FeatureFullFP16,
+ FeatureDotProd,
+ FeatureRCPC,
+ FeaturePerfMon
+ ]>;
+
def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
"Cyclone", [
FeatureAlternateSExtLoadCVTF32Pattern,
@@ -382,13 +406,15 @@ def : ProcessorModel<"generic", NoSchedM
FeaturePostRAScheduler
]>;
-// FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
+// FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53.
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
+def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
-// FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
+// FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57.
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
+def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon Aug 21 01:43:06 2017
@@ -451,7 +451,7 @@ def SDOTIDX4S : BaseSIMDThreeSameVectorD
}
let Predicates = [HasRCPC] in {
- // v8.3 Release Consistent Processor Consistent support
+ // v8.3 Release Consistent Processor Consistent support, optional in v8.2.
def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;
def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;
def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Mon Aug 21 01:43:06 2017
@@ -130,10 +130,10 @@ void AArch64Subtarget::initializePropert
case CortexA53:
PrefFunctionAlignment = 3;
break;
+ case CortexA55: break;
case CortexA72:
- PrefFunctionAlignment = 4;
- break;
case CortexA73:
+ case CortexA75:
PrefFunctionAlignment = 4;
break;
case Others: break;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Mon Aug 21 01:43:06 2017
@@ -41,9 +41,11 @@ public:
Others,
CortexA35,
CortexA53,
+ CortexA55,
CortexA57,
CortexA72,
CortexA73,
+ CortexA75,
Cyclone,
ExynosM1,
Falkor,
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Mon Aug 21 01:43:06 2017
@@ -435,12 +435,16 @@ def ProcA35 : SubtargetFeature<"a35"
"Cortex-A35 ARM processors", []>;
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors", []>;
+def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
+ "Cortex-A55 ARM processors", []>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", []>;
def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
"Cortex-A72 ARM processors", []>;
def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
"Cortex-A73 ARM processors", []>;
+def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
+ "Cortex-A75 ARM processors", []>;
def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
"Qualcomm Krait processors", []>;
@@ -921,6 +925,11 @@ def : ProcNoItin<"cortex-a53",
FeatureCRC,
FeatureFPAO]>;
+def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55,
+ FeatureHWDivThumb,
+ FeatureHWDivARM,
+ FeatureDotProd]>;
+
def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
FeatureHWDivThumb,
FeatureHWDivARM,
@@ -942,6 +951,11 @@ def : ProcNoItin<"cortex-a73",
FeatureCrypto,
FeatureCRC]>;
+def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75,
+ FeatureHWDivThumb,
+ FeatureHWDivARM,
+ FeatureDotProd]>;
+
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureHasRetAddrStack,
FeatureNEONForFP,
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Aug 21 01:43:06 2017
@@ -279,9 +279,11 @@ void ARMSubtarget::initSubtargetFeatures
case CortexA32:
case CortexA35:
case CortexA53:
+ case CortexA55:
case CortexA57:
case CortexA72:
case CortexA73:
+ case CortexA75:
case CortexR4:
case CortexR4F:
case CortexR5:
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Aug 21 01:43:06 2017
@@ -53,10 +53,12 @@ protected:
CortexA35,
CortexA5,
CortexA53,
+ CortexA55,
CortexA57,
CortexA7,
CortexA72,
CortexA73,
+ CortexA75,
CortexA8,
CortexA9,
CortexM3,
Modified: llvm/trunk/test/CodeGen/AArch64/cpus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cpus.ll?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/cpus.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/cpus.ll Mon Aug 21 01:43:06 2017
@@ -4,9 +4,11 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a55 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a75 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
Modified: llvm/trunk/test/CodeGen/AArch64/remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/remat.ll?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/remat.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/remat.ll Mon Aug 21 01:43:06 2017
@@ -1,8 +1,10 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s
Modified: llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s Mon Aug 21 01:43:06 2017
@@ -1,4 +1,6 @@
// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
+// RUN: llvm-mc -triple aarch64 -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
Modified: llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s Mon Aug 21 01:43:06 2017
@@ -1,4 +1,7 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a75 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s 2>&1 | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
Modified: llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s (original)
+++ llvm/trunk/test/MC/ARM/armv8.2a-dotprod-a32.s Mon Aug 21 01:43:06 2017
@@ -1,4 +1,6 @@
// RUN: llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK
+// RUN: llvm-mc -triple arm -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
+// RUN: llvm-mc -triple arm -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
// RUN: not llvm-mc -triple arm -mattr=-dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
Modified: llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s (original)
+++ llvm/trunk/test/MC/ARM/armv8.2a-dotprod-t32.s Mon Aug 21 01:43:06 2017
@@ -1,4 +1,6 @@
// RUN: llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK
+// RUN: llvm-mc -triple thumb -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
+// RUN: llvm-mc -triple thumb -mcpu=cortex-a55 -show-encoding < %s | FileCheck %s --check-prefix=CHECK
// RUN: not llvm-mc -triple thumb -mattr=-dotprod -show-encoding < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
Modified: llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt Mon Aug 21 01:43:06 2017
@@ -1,4 +1,6 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+dotprod --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-dotprod --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
0x20,0x94,0x82,0x2e
Modified: llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt Mon Aug 21 01:43:06 2017
@@ -1,4 +1,7 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a75 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-a55 --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a -mattr=+rcpc --disassemble < %s | FileCheck %s
# CHECK: ldaprb w0, [x0]
# CHECK: ldaprh w0, [x0]
Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=311316&r1=311315&r2=311316&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp Mon Aug 21 01:43:06 2017
@@ -218,6 +218,12 @@ TEST(TargetParserTest, testARMCPU) {
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A"));
+ EXPECT_TRUE(testARMCPU("cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
+ ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
+ ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+ ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
+ ARM::AEK_RAS | ARM::AEK_DOTPROD,
+ "8.2-A"));
EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -233,6 +239,12 @@ TEST(TargetParserTest, testARMCPU) {
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-A"));
+ EXPECT_TRUE(testARMCPU("cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
+ ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
+ ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+ ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
+ ARM::AEK_RAS | ARM::AEK_DOTPROD,
+ "8.2-A"));
EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -515,6 +527,7 @@ TEST(TargetParserTest, ARMArchExtFeature
{"virt", "novirt", nullptr, nullptr},
{"fp16", "nofp16", "+fullfp16", "-fullfp16"},
{"ras", "noras", "+ras", "-ras"},
+ {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"os", "noos", nullptr, nullptr},
{"iwmmxt", "noiwmmxt", nullptr, nullptr},
{"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
@@ -651,6 +664,12 @@ TEST(TargetParserTest, testAArch64CPU) {
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(
+ "cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
+ "8.2-A"));
+ EXPECT_TRUE(testAArch64CPU(
"cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD, "8-A"));
@@ -663,6 +682,12 @@ TEST(TargetParserTest, testAArch64CPU) {
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(
+ "cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
+ "8.2-A"));
+ EXPECT_TRUE(testAArch64CPU(
"cyclone", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, "8-A"));
EXPECT_TRUE(testAArch64CPU(
@@ -740,12 +765,16 @@ TEST(TargetParserTest, testAArch64Extens
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a53",
AArch64::ArchKind::INVALID, "ras"));
+ EXPECT_TRUE(testAArch64Extension("cortex-a55",
+ AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a57",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a72",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cortex-a73",
AArch64::ArchKind::INVALID, "ras"));
+ EXPECT_TRUE(testAArch64Extension("cortex-a75",
+ AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("cyclone",
AArch64::ArchKind::INVALID, "ras"));
EXPECT_FALSE(testAArch64Extension("exynos-m1",
@@ -776,7 +805,8 @@ TEST(TargetParserTest, AArch64ExtensionF
unsigned Extensions = AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
AArch64::AEK_FP | AArch64::AEK_SIMD |
AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
- AArch64::AEK_RAS | AArch64::AEK_SVE;
+ AArch64::AEK_RAS | AArch64::AEK_SVE |
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC;
for (unsigned i = 0; i <= Extensions; i++)
EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features)
@@ -805,7 +835,9 @@ TEST(TargetParserTest, AArch64ArchExtFea
{"fp16", "nofp16", "+fullfp16", "-fullfp16"},
{"profile", "noprofile", "+spe", "-spe"},
{"ras", "noras", "+ras", "-ras"},
- {"sve", "nosve", "+sve", "-sve"}};
+ {"sve", "nosve", "+sve", "-sve"},
+ {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
+ {"rcpc", "norcpc", "+rcpc", "-rcpc" }};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),
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