[llvm] r311290 - [Mem2Reg] Modernize code a bit.
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 20 07:34:44 PDT 2017
Author: d0k
Date: Sun Aug 20 07:34:44 2017
New Revision: 311290
URL: http://llvm.org/viewvc/llvm-project?rev=311290&view=rev
Log:
[Mem2Reg] Modernize code a bit.
No functionality change intended.
Modified:
llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
Modified: llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp?rev=311290&r1=311289&r2=311290&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Sun Aug 20 07:34:44 2017
@@ -156,18 +156,11 @@ class RenamePassData {
public:
typedef std::vector<Value *> ValVector;
- RenamePassData() : BB(nullptr), Pred(nullptr), Values() {}
- RenamePassData(BasicBlock *B, BasicBlock *P, const ValVector &V)
- : BB(B), Pred(P), Values(V) {}
+ RenamePassData(BasicBlock *B, BasicBlock *P, ValVector V)
+ : BB(B), Pred(P), Values(std::move(V)) {}
BasicBlock *BB;
BasicBlock *Pred;
ValVector Values;
-
- void swap(RenamePassData &RHS) {
- std::swap(BB, RHS.BB);
- std::swap(Pred, RHS.Pred);
- Values.swap(RHS.Values);
- }
};
/// \brief This assigns and keeps a per-bb relative ordering of load/store
@@ -629,8 +622,8 @@ void PromoteMem2Reg::run() {
});
unsigned CurrentVersion = 0;
- for (unsigned i = 0, e = PHIBlocks.size(); i != e; ++i)
- QueuePhiNode(PHIBlocks[i], AllocaNum, CurrentVersion);
+ for (BasicBlock *BB : PHIBlocks)
+ QueuePhiNode(BB, AllocaNum, CurrentVersion);
}
if (Allocas.empty())
@@ -652,8 +645,7 @@ void PromoteMem2Reg::run() {
std::vector<RenamePassData> RenamePassWorkList;
RenamePassWorkList.emplace_back(&F.front(), nullptr, std::move(Values));
do {
- RenamePassData RPD;
- RPD.swap(RenamePassWorkList.back());
+ RenamePassData RPD = std::move(RenamePassWorkList.back());
RenamePassWorkList.pop_back();
// RenamePass may add new worklist entries.
RenamePass(RPD.BB, RPD.Pred, RPD.Values, RenamePassWorkList);
@@ -663,9 +655,7 @@ void PromoteMem2Reg::run() {
Visited.clear();
// Remove the allocas themselves from the function.
- for (unsigned i = 0, e = Allocas.size(); i != e; ++i) {
- Instruction *A = Allocas[i];
-
+ for (Instruction *A : Allocas) {
// If there are any uses of the alloca instructions left, they must be in
// unreachable basic blocks that were not processed by walking the dominator
// tree. Just delete the users now.
@@ -675,8 +665,8 @@ void PromoteMem2Reg::run() {
}
// Remove alloca's dbg.declare instrinsics from the function.
- for (unsigned i = 0, e = AllocaDbgDeclares.size(); i != e; ++i)
- if (DbgDeclareInst *DDI = AllocaDbgDeclares[i])
+ for (DbgDeclareInst *DDI : AllocaDbgDeclares)
+ if (DDI)
DDI->eraseFromParent();
// Loop over all of the PHI nodes and see if there are any that we can get
@@ -762,8 +752,8 @@ void PromoteMem2Reg::run() {
while ((SomePHI = dyn_cast<PHINode>(BBI++)) &&
SomePHI->getNumIncomingValues() == NumBadPreds) {
Value *UndefVal = UndefValue::get(SomePHI->getType());
- for (unsigned pred = 0, e = Preds.size(); pred != e; ++pred)
- SomePHI->addIncoming(UndefVal, Preds[pred]);
+ for (BasicBlock *Pred : Preds)
+ SomePHI->addIncoming(UndefVal, Pred);
}
}
@@ -834,9 +824,7 @@ void PromoteMem2Reg::ComputeLiveInBlocks
// Since the value is live into BB, it is either defined in a predecessor or
// live into it to. Add the preds to the worklist unless they are a
// defining block.
- for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
- BasicBlock *P = *PI;
-
+ for (BasicBlock *P : predecessors(BB)) {
// The value is not live into a predecessor if it defines the value.
if (DefBlocks.count(P))
continue;
More information about the llvm-commits
mailing list