[PATCH] D36663: [X86][Haswell] Updating HSW instruction scheduling information

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added inline comments.


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Comment at: lib/Target/X86/X86SchedHaswell.td:3156
+}
+def: InstRW<[HWWriteResGroup74], (instregex "IMUL(16|32|64)r")>;
+def: InstRW<[HWWriteResGroup74], (instregex "MUL(16|32|64)r")>;
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craig.topper wrote:
> Can you recheck this. I believe the following
> 
> MUL16r/IMUL16r - 4 uops
> MUL32r/IMUL32r - 3 uops
> IMUL64r/IMUL64r - 2 uops
> MULX64rr - 2 uops
Will re-check with the architects to verify.


Repository:
  rL LLVM

https://reviews.llvm.org/D36663