[PATCH] D36845: [X86] Allow xacquire/xrelease prefixes

[coby via Phabricator via llvm-commits]

coby updated this revision to Diff 111876.
coby added a comment.

> @RKSimon : Please can you add tests for the intel-syntax acquire/release as well?

Added.


Repository:
  rL LLVM

https://reviews.llvm.org/D36845

Files:
  lib/Target/X86/AsmParser/X86AsmParser.cpp
  lib/Target/X86/X86InstrInfo.td
  test/MC/X86/intel-syntax-encoding.s
  test/MC/X86/x86-64.s


Index: lib/Target/X86/AsmParser/X86AsmParser.cpp
===================================================================
--- lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2457,11 +2457,21 @@
   Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
 
   // Determine whether this is an instruction prefix.
-  bool isPrefix =
-    Name == "lock" || Name == "rep" ||
-    Name == "repe" || Name == "repz" ||
-    Name == "repne" || Name == "repnz" ||
-    Name == "rex64" || Name == "data16" || Name == "data32";
+  // FIXME:
+  // Enhace prefixes integrity robustness. for example, following forms
+  // are currently tolerated:
+  // repz repnz <insn>    ; GAS errors for the use of two similar prefixes
+  // lock addq %rax, %rbx ; Destination operand must be of memory type
+  // xacquire <insn>      ; xacquire must be accompanied by 'lock'
+  bool isPrefix = StringSwitch<bool>(Name)
+    .Cases("lock",
+           "rep",       "repe",
+           "repz",      "repne",
+           "repnz",     "rex64",
+           "data32",    "data16",   true)
+    .Cases("xacquire",  "xrelease", true)
+    .Cases("acquire",   "release",  isParsingIntelSyntax())
+    .Default(false);
 
   bool CurlyAsEndOfStatement = false;
   // This does the actual operand parsing.  Don't parse any more if we have a
Index: lib/Target/X86/X86InstrInfo.td
===================================================================
--- lib/Target/X86/X86InstrInfo.td
+++ lib/Target/X86/X86InstrInfo.td
@@ -2848,6 +2848,10 @@
 def : MnemonicAlias<"ud2a",  "ud2",  "att">;
 def : MnemonicAlias<"verrw", "verr", "att">;
 
+// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release'
+def : MnemonicAlias<"acquire", "xacquire", "intel">;
+def : MnemonicAlias<"release", "xrelease", "intel">;
+
 // System instruction aliases.
 def : MnemonicAlias<"iret",    "iretw",    "att">, Requires<[In16BitMode]>;
 def : MnemonicAlias<"iret",    "iretl",    "att">, Requires<[Not16BitMode]>;
Index: test/MC/X86/intel-syntax-encoding.s
===================================================================
--- test/MC/X86/intel-syntax-encoding.s
+++ test/MC/X86/intel-syntax-encoding.s
@@ -52,6 +52,15 @@
 // CHECK: encoding: [0x48,0x83,0xf8,0xf4]
 	cmp	rax, -12
 
+  acquire lock add [rax], rax
+// CHECK: encoding: [0xf2]
+// CHECK: encoding: [0xf0]
+// CHECK: encoding: [0x48,0x01,0x00]
+  release lock add [rax], rax
+// CHECK: encoding: [0xf3]
+// CHECK: encoding: [0xf0]
+// CHECK: encoding: [0x48,0x01,0x00]
+
 LBB0_3:
 // CHECK: encoding: [0xeb,A]
 	jmp	LBB0_3
Index: test/MC/X86/x86-64.s
===================================================================
--- test/MC/X86/x86-64.s
+++ test/MC/X86/x86-64.s
@@ -930,6 +930,21 @@
 // CHECK: xorq %rsi, (%rdi)
 // CHECK: encoding: [0x48,0x31,0x37]
 
+xacquire lock addq %rax, (%rax)
+// CHECK: xacquire
+// CHECK: encoding: [0xf2]
+// CHECK: lock
+// CHECK: encoding: [0xf0]
+// CHECK: addq %rax, (%rax)
+// CHECK: encoding: [0x48,0x01,0x00]
+
+xrelease lock addq %rax, (%rax)
+// CHECK: xrelease
+// CHECK: encoding: [0xf3]
+// CHECK: lock
+// CHECK: encoding: [0xf0]
+// CHECK: addq %rax, (%rax)
+// CHECK: encoding: [0x48,0x01,0x00]
 
 // rdar://8033482
 rep movsl


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