[llvm] r311206 - [InstCombine] Teach ComputeNumSignBitsImpl to handle integer multiply instruction.
Amjad Aboud via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 18 15:56:55 PDT 2017
Author: aaboud
Date: Fri Aug 18 15:56:55 2017
New Revision: 311206
URL: http://llvm.org/viewvc/llvm-project?rev=311206&view=rev
Log:
[InstCombine] Teach ComputeNumSignBitsImpl to handle integer multiply instruction.
Differential Revision: https://reviews.llvm.org/D36679
Modified:
llvm/trunk/lib/Analysis/ValueTracking.cpp
llvm/trunk/test/Transforms/InstCombine/trunc.ll
Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=311206&r1=311205&r2=311206&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Fri Aug 18 15:56:55 2017
@@ -2196,6 +2196,17 @@ static unsigned ComputeNumSignBitsImpl(c
if (Tmp == 1) return 1; // Early out.
return std::min(Tmp, Tmp2)-1;
+ case Instruction::Mul: {
+ // The output of the Mul can be at most twice the valid bits in the inputs.
+ unsigned SignBitsOp0 = ComputeNumSignBits(U->getOperand(0), Depth + 1, Q);
+ if (SignBitsOp0 == 1) return 1; // Early out.
+ unsigned SignBitsOp1 = ComputeNumSignBits(U->getOperand(1), Depth + 1, Q);
+ if (SignBitsOp1 == 1) return 1;
+ unsigned OutValidBits =
+ (TyBits - SignBitsOp0 + 1) + (TyBits - SignBitsOp1 + 1);
+ return OutValidBits > TyBits ? 1 : TyBits - OutValidBits + 1;
+ }
+
case Instruction::PHI: {
const PHINode *PN = cast<PHINode>(U);
unsigned NumIncomingValues = PN->getNumIncomingValues();
Modified: llvm/trunk/test/Transforms/InstCombine/trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/trunc.ll?rev=311206&r1=311205&r2=311206&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/trunc.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/trunc.ll Fri Aug 18 15:56:55 2017
@@ -89,6 +89,21 @@ define i32 @test6(i64 %A) {
ret i32 %D
}
+define i16 @ashr_mul(i8 %X, i8 %Y) {
+; CHECK-LABEL: @ashr_mul(
+; CHECK-NEXT: [[A:%.*]] = sext i8 %X to i16
+; CHECK-NEXT: [[B:%.*]] = sext i8 %Y to i16
+; CHECK-NEXT: [[C:%.*]] = mul nsw i16 [[A]], [[B]]
+; CHECK-NEXT: [[D:%.*]] = ashr i16 [[C]], 8
+; CHECK-NEXT: ret i16 [[D]]
+ %A = sext i8 %X to i20
+ %B = sext i8 %Y to i20
+ %C = mul i20 %A, %B
+ %D = ashr i20 %C, 8
+ %E = trunc i20 %D to i16
+ ret i16 %E
+}
+
define i32 @trunc_ashr(i32 %X) {
; CHECK-LABEL: @trunc_ashr(
; CHECK-NEXT: [[B:%.*]] = or i32 [[X:%.*]], -2147483648
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