[llvm] r310876 - IPRA: Allow target to enable IPRA by default

[Daniel Sanders via llvm-commits]

Hi Matt,

This change disabled IPRA on one of our out-of-tree targets. We are setting TM.Options.EnableIPRA but then the default path from this code is overriding our settings. I've worked around this locally by changing:
> +    // If not explicitly specified, use target default.
> +    TM.Options.EnableIPRA = TM.useIPRA();
to use |= instead of =. Should we make this change upstream too or should we fix it another way?

Thanks

> On 14 Aug 2017, at 20:54, Matt Arsenault via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: arsenm
> Date: Mon Aug 14 12:54:47 2017
> New Revision: 310876
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=310876&view=rev
> Log:
> IPRA: Allow target to enable IPRA by default
> 
> Modified:
>    llvm/trunk/include/llvm/Target/TargetMachine.h
>    llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
>    llvm/trunk/lib/Target/TargetMachine.cpp
> 
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=310876&r1=310875&r2=310876&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Aug 14 12:54:47 2017
> @@ -259,6 +259,12 @@ public:
>   /// PEI. If false (virtual-register machines), then callee-save register
>   /// spilling and scavenging are not needed or used.
>   virtual bool usesPhysRegsForPEI() const { return true; }
> +
> +  /// True if the target wants to use interprocedural register allocation by
> +  /// default. The -enable-ipra flag can be used to override this.
> +  virtual bool useIPRA() const {
> +    return false;
> +  }
> };
> 
> /// This class describes a target machine that is implemented with the LLVM
> 
> Modified: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=310876&r1=310875&r2=310876&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp (original)
> +++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp Mon Aug 14 12:54:47 2017
> @@ -47,6 +47,9 @@
> 
> using namespace llvm;
> 
> +cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
> +                         cl::desc("Enable interprocedural register allocation "
> +                                  "to reduce load/store at procedure calls."));
> static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
>     cl::desc("Disable Post Regalloc Scheduler"));
> static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
> @@ -362,6 +365,13 @@ TargetPassConfig::TargetPassConfig(LLVMT
>   if (StringRef(PrintMachineInstrs.getValue()).equals(""))
>     TM.Options.PrintMachineCode = true;
> 
> +  if (EnableIPRA.getNumOccurrences())
> +    TM.Options.EnableIPRA = EnableIPRA;
> +  else {
> +    // If not explicitly specified, use target default.
> +    TM.Options.EnableIPRA = TM.useIPRA();
> +  }
> +
>   if (TM.Options.EnableIPRA)
>     setRequiresCodeGenSCCOrder();
> 
> 
> Modified: llvm/trunk/lib/Target/TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=310876&r1=310875&r2=310876&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/TargetMachine.cpp Mon Aug 14 12:54:47 2017
> @@ -31,10 +31,6 @@
> #include "llvm/Target/TargetSubtargetInfo.h"
> using namespace llvm;
> 
> -cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
> -                         cl::desc("Enable interprocedural register allocation "
> -                                  "to reduce load/store at procedure calls."));
> -
> //---------------------------------------------------------------------------
> // TargetMachine Class
> //
> @@ -45,8 +41,6 @@ TargetMachine::TargetMachine(const Targe
>     : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU),
>       TargetFS(FS), AsmInfo(nullptr), MRI(nullptr), MII(nullptr), STI(nullptr),
>       RequireStructuredCFG(false), DefaultOptions(Options), Options(Options) {
> -  if (EnableIPRA.getNumOccurrences())
> -    this->Options.EnableIPRA = EnableIPRA;
> }
> 
> TargetMachine::~TargetMachine() {
> 
> 
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