[PATCH] D36837: [SLP] Fix for PR34219, part 1: Use minimal alignment for vectorized loads.

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added inline comments.


================
Comment at: test/Transforms/SLPVectorizer/X86/sitofp.ll:88
 ; AVX512-LABEL: @sitofp_4i64_4f64(
-; AVX512-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
+; AVX512-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 8
 ; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
----------------
RKSimon wrote:
> We know src64 is 64-byte aligned, and the base load (%ld0) is 64-byte aligned - so why do you have to assume 8-byte?
Agree, dropping these patches.


https://reviews.llvm.org/D36837