[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Geoff Berry via Phabricator via llvm-commits]

gberry added a comment.

Something like the below is what I meant by transforming the uses instead.  The FIXME comment needs to be addressed, but I think it should do what you want and catch the cases where not all uses are vreg COPYs:

In AArch64DAGToDAGISel::Select, instead of chaning the Constant case, add the following:

  case ISD::CopyToReg: {
    // Special case for copy of zero to avoid a double copy.
    // FIXME: check dst is virt reg and regclass is okay
    SDNode *CopyVal = Node->getOperand(2).getNode();
    if (ConstantSDNode *CopyValConst = dyn_cast<ConstantSDNode>(CopyVal))
      if (CopyValConst->isNullValue()) {
        unsigned ZeroReg;
        EVT ZeroVT = CopyValConst->getValueType(0);
        if (ZeroVT == MVT::i32)
          ZeroReg = AArch64::WZR;
        else if (ZeroVT == MVT::i64)
          ZeroReg = AArch64::XZR;
        else
          break;
  
        SDValue ZeroRegVal = CurDAG->getRegister(ZeroReg, ZeroVT);
        SDValue New = CurDAG->getNode(ISD::CopyToReg, SDLoc(Node), MVT::Other,
                                      Node->getOperand(0), Node->getOperand(1),
                                      ZeroRegVal);
        ReplaceNode(Node, New.getNode());
        return;
      }
    break;
  }


Repository:
  rL LLVM

https://reviews.llvm.org/D36104