[PATCH] D34396: Adding code padding for performance stability - first policy (BranchesWithSameTargetAvoidancePolicy)

[Omer Paparo Bivas via Phabricator via llvm-commits]

opaparo added a comment.

In https://reviews.llvm.org/D34396#843773, @iteratee wrote:

> Do you plan on doing something similar for the DSB decode cache issues that occasionally arise?
>  Specifically this: https://bugs.llvm.org/show_bug.cgi?id=5615


Yes, I have implemented a MCCodePaddingPolicy that addresses this issue. I will upload that patch once the infrastructure is accepted and committed.



================
Comment at: lib/Target/X86/MCTargetDesc/X86MCCodePadder.cpp:37
+
+  if (CPU != "sandybridge" && CPU != "corei7-avx" && CPU != "ivybridge" &&
+      CPU != "core-avx-i" && CPU != "haswell" && CPU != "core-avx2" &&
----------------
iteratee wrote:
> Should this be a feature of TargetMachine so that this list doesn't go out of date?
It should. I am working on that, will upload the patch ASAP.


https://reviews.llvm.org/D34396