[PATCH] D23566: [RISCV 8/10] Add support for all RV32I instructions
Alex Bradbury via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 16 05:36:01 PDT 2017
asb added a comment.
I should have said - please do take a look at the handling of the fence arguments in RISCVAsmParser. I've actually avoided adding a new RISCVOperand type or directly modifying the operand parsing machinery (as AArch64 does for CondCodes). Allowing whatever is there to be parsed, then working out if it's valid or not seemed to more in line with the rest of the MC assembler parser.
https://reviews.llvm.org/D23566
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