[PATCH] D36679: [InstCombine] Added support for: trunc(ashr(mul(sext(...), sext(...))) -> ashr(mul(...))

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Can we have the ashr fix as a separate patch before the mul patch? If yes, make tests for just that diff and split this up?



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Comment at: lib/Transforms/InstCombine/InstCombineCasts.cpp:378
+    //       similar to sign bit of the truncate type.
+    if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
+      uint32_t OrigBitWidth = OrigTy->getScalarSizeInBits();
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Over in D36763, we're going to (or maybe already have) made the other shift cases splat-vector-friendly. Can you do the same here and add a vector test?


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Comment at: lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:468
     if (match(I->getOperand(1), m_APInt(SA))) {
-      uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
+      uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
 
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Why change this in this patch? Seem like that might be better as just 'unsigned', but either way, I think it's an independent diff.


https://reviews.llvm.org/D36679