[PATCH] D36706: DAGCombiner: Add form of isFPExtFree to check uses

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 111059.
arsenm added a comment.

Just add an opcode field to be sure it's only used here. It's a lot simpler patch and sufficient for my needs rather than updating all of the individual places this is needed


https://reviews.llvm.org/D36706

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8993,7 +8993,7 @@
   // Always prefer FMAD to FMA for precision.
   unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
   bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
-  bool LookThroughFPExt = TLI.isFPExtFree(VT);
+  bool LookThroughFPExt = TLI.isFPExtFree(PreferredFusedOpcode, VT);
 
   // Is the node an FMUL and contractable either due to global flags or
   // SDNodeFlags.
Index: include/llvm/Target/TargetLowering.h
===================================================================
--- include/llvm/Target/TargetLowering.h
+++ include/llvm/Target/TargetLowering.h
@@ -2125,6 +2125,15 @@
     return false;
   }
 
+  /// Return true if an fpext operation input to an \p Opcode operation is free
+  /// (for instance, because half-precision floating-point numbers are
+  /// implicitly extended to float-precision) for an FMA instruction.
+  virtual bool isFPExtFree(unsigned Opcode, EVT DestVT) const {
+    // TODO: SrcVT may be useful.
+    assert(VT.isFloatingPoint());
+    return false;
+  }
+
   /// Return true if folding a vector load into ExtVal (a sign, zero, or any
   /// extend node) is profitable.
   virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }


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