[llvm] r310480 - [AArch64] Assembler support for the ARMv8.2a dot product instructions
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 09:27:07 PDT 2017
On Fri, Aug 11, 2017 at 2:15 AM, Sjoerd Meijer <Sjoerd.Meijer at arm.com> wrote:
> Hi Ahmed,
>
>
>
> I also didn’t realise this, but now I think the best way to look at this
> table is as some sensible defaults for the architecture. What I mean is,
> crypto is optional, and strictly speaking even FP is optional, but it is of
> course sensible to have them on by default. What exactly constitutes an
> architecture is a bit difficult to tell with all the (non)optional
> extensions. However, I will remove dot product from this base extensions
> list as it was a late addition to ARMv8.2a (and also optional). Thanks for
> checking and reviewing this.
>
>
>
> There are a few more odd things about this table. For example, I am also
> wondering why LSE is listed there while it is non-optional; it should just
> be implied by v8.1a.
>
> It is actually very high on our agenda to do some serious work refactoring
> here and we will send an RFC to the list first what we plan to do.
I'm glad to hear that, thanks for the work!
-Ahmed
>
>
> Cheers,
>
> Sjoerd.
>
>
>
> From: Sjoerd Meijer
> Sent: 10 August 2017 22:17
> To: Ahmed Bougacha
>
>
> Cc: llvm-commits
> Subject: Re: [llvm] r310480 - [AArch64] Assembler support for the ARMv8.2a
> dot product instructions
>
>
>
> Hi Ahmed,
>
>
>
> Just to let you know I will check the armv8.2a arch description my tomorrow
> morning and will let you know.
>
> And yes, the target parser support was added so that we can expose it to
> user and do things like -march=armv8.2a+dotprod. I will put the Clang patch
> up for review soon; I hope to do that tomorrow. I probably should have
> mentioned that in this commit.
>
>
>
> Thanks,
>
> Sjoerd.
>
> ________________________________
>
> From: Ahmed Bougacha <ahmed.bougacha at gmail.com>
> Sent: 10 August 2017 21:02:38
> To: Sjoerd Meijer
> Cc: llvm-commits
> Subject: Re: [llvm] r310480 - [AArch64] Assembler support for the ARMv8.2a
> dot product instructions
>
>
>
> Hi Sjoerd,
>
> On Wed, Aug 9, 2017 at 7:59 AM, Sjoerd Meijer via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>> Author: sjoerdmeijer
>> Date: Wed Aug 9 07:59:54 2017
>> New Revision: 310480
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=310480&view=rev
>> Log:
>> [AArch64] Assembler support for the ARMv8.2a dot product instructions
>>
>> Dot product is an optional ARMv8.2a extension, see also the public
>> architecture
>> specification here:
>>
>> https://developer.arm.com/products/architecture/a-profile/exploration-tools.
>> This patch adds AArch64 assembler support for these dot product
>> instructions.
>>
>> Differential Revision: https://reviews.llvm.org/D36515
>>
>> Added:
>> llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s
>> llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s
>> llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt
>> Modified:
>> llvm/trunk/include/llvm/Support/AArch64TargetParser.def
>> llvm/trunk/include/llvm/Support/TargetParser.h
>> llvm/trunk/lib/Target/AArch64/AArch64.td
>> llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
>> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
>> llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
>> llvm/trunk/test/MC/AArch64/neon-diagnostics.s
>>
>> Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
>> +++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Wed Aug 9
>> 07:59:54 2017
>> @@ -28,7 +28,8 @@ AARCH64_ARCH("armv8.1-a", ARMV8_1A, "8.1
>> AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a",
>> ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
>> (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
>> - AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
>> + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
>> + AArch64::AEK_DOTPROD))
>
> If the feature is optional with v8.2a, why is it here? We use these
> "base" extensions as the mandatory extensions constituting the arch,
> no?
>
> Additionally, why do we need the support in TargetParser in the first
> place? My understanding is, exposing the feature here is only
> necessary to be able to expose it to users in the clang driver (via
> preprocessor macros and/or -m flags). Do you plan to add that too?
>
> Thanks!
> -Ahmed
>
>> #undef AARCH64_ARCH
>>
>> #ifndef AARCH64_ARCH_EXT_NAME
>> @@ -40,6 +41,7 @@ AARCH64_ARCH_EXT_NAME("none", AArch6
>> AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc",
>> "-crc")
>> AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse",
>> "-lse")
>> AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO,
>> "+crypto","-crypto")
>> +AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD,
>> "+dotprod","-dotprod")
>> AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8",
>> "-fp-armv8")
>> AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon",
>> "-neon")
>> AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16",
>> "-fullfp16")
>>
>> Modified: llvm/trunk/include/llvm/Support/TargetParser.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/include/llvm/Support/TargetParser.h (original)
>> +++ llvm/trunk/include/llvm/Support/TargetParser.h Wed Aug 9 07:59:54
>> 2017
>> @@ -166,7 +166,8 @@ enum ArchExtKind : unsigned {
>> AEK_PROFILE = 0x40,
>> AEK_RAS = 0x80,
>> AEK_LSE = 0x100,
>> - AEK_SVE = 0x200
>> + AEK_SVE = 0x200,
>> + AEK_DOTPROD = 0x400
>> };
>>
>> StringRef getCanonicalArchName(StringRef Arch);
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64.td Wed Aug 9 07:59:54 2017
>> @@ -122,6 +122,10 @@ def FeatureUseRSqrt : SubtargetFeature<
>> "use-reciprocal-square-root", "UseRSqrt", "true",
>> "Use the reciprocal square root approximation">;
>>
>> +def FeatureDotProd : SubtargetFeature<
>> + "dotprod", "HasDotProd", "true",
>> + "Enable dot product support">;
>> +
>> def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
>> "NegativeImmediates", "false",
>> "Convert immediates and
>> instructions "
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Wed Aug 9
>> 07:59:54 2017
>> @@ -4374,6 +4374,12 @@ class BaseSIMDThreeSameVectorTied<bit Q,
>> let Inst{4-0} = Rd;
>> }
>>
>> +class BaseSIMDThreeSameVectorDot<bit Q, bit U, string asm, string kind1,
>> + string kind2> :
>> + BaseSIMDThreeSameVector<Q, U, 0b100, 0b10010, V128, asm, kind1,
>> [] > {
>> + let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ",
>> $Rm" # kind2 # "}");
>> +}
>> +
>> // All operand sizes distinguished in the encoding.
>> multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
>> SDPatternOperator OpNode> {
>> @@ -6801,6 +6807,16 @@ class BaseSIMDIndexedTied<bit Q, bit U,
>> let Inst{4-0} = Rd;
>> }
>>
>> +// ARMv8.2 Index Dot product instructions
>> +class BaseSIMDThreeSameVectorDotIndex<bit Q, bit U, string asm, string
>> dst_kind,
>> + string lhs_kind, string rhs_kind> :
>> + BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, V128, V128, V128,
>> VectorIndexS,
>> + asm, "", dst_kind, lhs_kind, rhs_kind, []> {
>> + bits<2> idx;
>> + let Inst{21} = idx{0}; // L
>> + let Inst{11} = idx{1}; // H
>> +}
>> +
>> multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
>> SDPatternOperator OpNode> {
>> let Predicates = [HasNEON, HasFullFP16] in {
>> @@ -9596,6 +9612,7 @@ multiclass STOPregister<string asm, stri
>>
>>
>> //----------------------------------------------------------------------------
>> // Allow the size specifier tokens to be upper case, not just lower.
>> +def : TokenAlias<".4B", ".4b">; // Add dot product
>> def : TokenAlias<".8B", ".8b">;
>> def : TokenAlias<".4H", ".4h">;
>> def : TokenAlias<".2S", ".2s">;
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Wed Aug 9 07:59:54
>> 2017
>> @@ -24,6 +24,8 @@ def HasNEON : Predicate<"Subtar
>> AssemblerPredicate<"FeatureNEON",
>> "neon">;
>> def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
>> AssemblerPredicate<"FeatureCrypto",
>> "crypto">;
>> +def HasDotProd : Predicate<"Subtarget->hasDotProd()">,
>> + AssemblerPredicate<"FeatureDotProd",
>> "dotprod">;
>> def HasCRC : Predicate<"Subtarget->hasCRC()">,
>> AssemblerPredicate<"FeatureCRC", "crc">;
>> def HasLSE : Predicate<"Subtarget->hasLSE()">,
>> @@ -432,6 +434,18 @@ def ISB : CRmSystemI<barrier_op, 0b110
>> [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
>> }
>>
>> +// ARMv8.2 Dot Product
>> +let Predicates = [HasDotProd] in {
>> +def UDOT2S : BaseSIMDThreeSameVectorDot<0, 1, "udot", ".2s", ".8b">;
>> +def SDOT2S : BaseSIMDThreeSameVectorDot<0, 0, "sdot", ".2s", ".8b">;
>> +def UDOT4S : BaseSIMDThreeSameVectorDot<1, 1, "udot", ".4s", ".16b">;
>> +def SDOT4S : BaseSIMDThreeSameVectorDot<1, 0, "sdot", ".4s", ".16b">;
>> +def UDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 1, "udot", ".2s",
>> ".8b", ".4b">;
>> +def SDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 0, "sdot", ".2s",
>> ".8b", ".4b">;
>> +def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s",
>> ".16b", ".4b">;
>> +def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s",
>> ".16b", ".4b">;
>> +}
>> +
>> def : InstAlias<"clrex", (CLREX 0xf)>;
>> def : InstAlias<"isb", (ISB 0xf)>;
>>
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Wed Aug 9 07:59:54
>> 2017
>> @@ -62,6 +62,7 @@ protected:
>> bool HasFPARMv8 = false;
>> bool HasNEON = false;
>> bool HasCrypto = false;
>> + bool HasDotProd = false;
>> bool HasCRC = false;
>> bool HasLSE = false;
>> bool HasRAS = false;
>> @@ -201,6 +202,7 @@ public:
>> bool hasFPARMv8() const { return HasFPARMv8; }
>> bool hasNEON() const { return HasNEON; }
>> bool hasCrypto() const { return HasCrypto; }
>> + bool hasDotProd() const { return HasDotProd; }
>> bool hasCRC() const { return HasCRC; }
>> bool hasLSE() const { return HasLSE; }
>> bool hasRAS() const { return HasRAS; }
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
>> (original)
>> +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Wed Aug
>> 9 07:59:54 2017
>> @@ -1810,6 +1810,8 @@ static bool isValidVectorKind(StringRef
>> .Case(".d", true)
>> // Needed for fp16 scalar pairwise reductions
>> .Case(".2h", true)
>> + // another special case for the ARMv8.2a dot product operand
>> + .Case(".4b", true)
>> .Default(false);
>> }
>>
>>
>> Added: llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s?rev=310480&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s (added)
>> +++ llvm/trunk/test/MC/AArch64/armv8.2a-dotprod-errors.s Wed Aug 9
>> 07:59:54 2017
>> @@ -0,0 +1,12 @@
>> +// RUN: not llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s
>> 2> %t
>> +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
>> +
>> +udot v0.2s, v1.8b, v2.4b[4]
>> +sdot v0.2s, v1.8b, v2.4b[4]
>> +udot v0.4s, v1.16b, v2.4b[4]
>> +sdot v0.4s, v1.16b, v2.4b[4]
>> +
>> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]
>> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]
>> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]
>> +// CHECK-ERROR: vector lane must be an integer in range [0, 3]
>>
>> Added: llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s?rev=310480&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s (added)
>> +++ llvm/trunk/test/MC/AArch64/armv8.2a-dotprod.s Wed Aug 9 07:59:54 2017
>> @@ -0,0 +1,60 @@
>> +// RUN: llvm-mc -triple aarch64 -mattr=+dotprod -show-encoding < %s |
>> FileCheck %s --check-prefix=CHECK-DOTPROD
>> +// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2>
>> %t
>> +// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
>> +
>> +udot v0.2s, v1.8b, v2.8b
>> +sdot v0.2s, v1.8b, v2.8b
>> +udot v0.4s, v1.16b, v2.16b
>> +sdot v0.4s, v1.16b, v2.16b
>> +udot v0.2s, v1.8b, v2.4b[0]
>> +sdot v0.2s, v1.8b, v2.4b[1]
>> +udot v0.4s, v1.16b, v2.4b[2]
>> +sdot v0.4s, v1.16b, v2.4b[3]
>> +
>> +// Check that the upper case types are aliases
>> +udot v0.2S, v1.8B, v2.4B[0]
>> +udot v0.4S, v1.16B, v2.4B[2]
>> +
>> +// CHECK-DOTPROD: udot v0.2s, v1.8b, v2.8b // encoding:
>> [0x20,0x94,0x82,0x2e]
>> +// CHECK-DOTPROD: sdot v0.2s, v1.8b, v2.8b // encoding:
>> [0x20,0x94,0x82,0x0e]
>> +// CHECK-DOTPROD: udot v0.4s, v1.16b, v2.16b // encoding:
>> [0x20,0x94,0x82,0x6e]
>> +// CHECK-DOTPROD: sdot v0.4s, v1.16b, v2.16b // encoding:
>> [0x20,0x94,0x82,0x4e]
>> +// CHECK-DOTPROD: udot v0.2s, v1.8b, v2.4b[0] // encoding:
>> [0x20,0xe0,0x82,0x2f]
>> +// CHECK-DOTPROD: sdot v0.2s, v1.8b, v2.4b[1] // encoding:
>> [0x20,0xe0,0xa2,0x0f]
>> +// CHECK-DOTPROD: udot v0.4s, v1.16b, v2.4b[2] // encoding:
>> [0x20,0xe8,0x82,0x6f]
>> +// CHECK-DOTPROD: sdot v0.4s, v1.16b, v2.4b[3] // encoding:
>> [0x20,0xe8,0xa2,0x4f]
>> +
>> +// CHECK-DOTPROD: udot v0.2s, v1.8b, v2.4b[0] // encoding:
>> [0x20,0xe0,0x82,0x2f]
>> +// CHECK-DOTPROD: udot v0.4s, v1.16b, v2.4b[2] // encoding:
>> [0x20,0xe8,0x82,0x6f]
>> +
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: udot v0.2s, v1.8b, v2.8b
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: sdot v0.2s, v1.8b, v2.8b
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: udot v0.4s, v1.16b, v2.16b
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: sdot v0.4s, v1.16b, v2.16b
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: udot v0.2s, v1.8b, v2.4b[0]
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: sdot v0.2s, v1.8b, v2.4b[1]
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: udot v0.4s, v1.16b, v2.4b[2]
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: sdot v0.4s, v1.16b, v2.4b[3]
>> +// CHECK-NO-DOTPROD: ^
>> +
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: udot v0.2S, v1.8B, v2.4B[0]
>> +// CHECK-NO-DOTPROD: ^
>> +// CHECK-NO-DOTPROD: error: instruction requires: dotprod
>> +// CHECK-NO-DOTPROD: udot v0.4S, v1.16B, v2.4B[2]
>> +// CHECK-NO-DOTPROD: ^
>>
>> Modified: llvm/trunk/test/MC/AArch64/neon-diagnostics.s
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-diagnostics.s?rev=310480&r1=310479&r2=310480&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/AArch64/neon-diagnostics.s (original)
>> +++ llvm/trunk/test/MC/AArch64/neon-diagnostics.s Wed Aug 9 07:59:54 2017
>> @@ -6395,8 +6395,7 @@
>> uzp1 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> uzp1 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp1 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp1 v0.4h, v1.2h, v2.2h
>> @@ -6416,8 +6415,7 @@
>> uzp2 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> uzp2 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp2 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp2 v0.4h, v1.2h, v2.2h
>> @@ -6437,8 +6435,7 @@
>> zip1 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> zip1 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip1 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip1 v0.4h, v1.2h, v2.2h
>> @@ -6454,12 +6451,11 @@
>> // CHECK-ERROR: [[@LINE-1]]:14: error: invalid operand for instruction
>>
>>
>> -\
>> +
>> zip2 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> zip2 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip2 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip2 v0.4h, v1.2h, v2.2h
>> @@ -6479,8 +6475,7 @@
>> trn1 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> trn1 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn1 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn1 v0.4h, v1.2h, v2.2h
>> @@ -6500,8 +6495,7 @@
>> trn2 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> trn2 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn2 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn2 v0.4h, v1.2h, v2.2h
>> @@ -6523,8 +6517,7 @@
>> uzp1 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> uzp1 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp1 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp1 v0.4h, v1.2h, v2.2h
>> @@ -6542,8 +6535,7 @@
>> uzp2 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> uzp2 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp2 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> uzp2 v0.4h, v1.2h, v2.2h
>> @@ -6561,8 +6553,7 @@
>> zip1 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> zip1 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip1 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip1 v0.4h, v1.2h, v2.2h
>> @@ -6584,8 +6575,7 @@
>> zip2 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> zip2 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip2 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> zip2 v0.4h, v1.2h, v2.2h
>> @@ -6606,8 +6596,7 @@
>> trn1 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> trn1 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn1 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn1 v0.4h, v1.2h, v2.2h
>> @@ -6627,8 +6616,7 @@
>> trn2 v0.16b, v1.8b, v2.8b
>> // CHECK-ERROR: [[@LINE-1]]:22: error: invalid operand for instruction
>> trn2 v0.8b, v1.4b, v2.4b
>> -// CHECK-ERROR: [[@LINE-1]]:21: error: invalid vector kind qualifier
>> -// CHECK-ERROR: [[@LINE-2]]:28: error: invalid vector kind qualifier
>> +// CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn2 v0.8h, v1.4h, v2.4h
>> // CHECK-ERROR: [[@LINE-1]]:21: error: invalid operand for instruction
>> trn2 v0.4h, v1.2h, v2.2h
>>
>> Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt?rev=310480&view=auto
>>
>> ==============================================================================
>> --- llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt (added)
>> +++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-dotprod.txt Wed Aug
>> 9 07:59:54 2017
>> @@ -0,0 +1,29 @@
>> +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+dotprod
>> --disassemble < %s | FileCheck %s
>> +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-dotprod
>> --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
>> +
>> +0x20,0x94,0x82,0x2e
>> +0x20,0x94,0x82,0x0e
>> +0x20,0x94,0x82,0x6e
>> +0x20,0x94,0x82,0x4e
>> +0x20,0xe0,0x82,0x2f
>> +0x20,0xe0,0xa2,0x0f
>> +0x20,0xe8,0x82,0x6f
>> +0x20,0xe8,0xa2,0x4f
>> +
>> +#CHECK: udot v0.2s, v1.8b, v2.8b
>> +#CHECK: sdot v0.2s, v1.8b, v2.8b
>> +#CHECK: udot v0.4s, v1.16b, v2.16b
>> +#CHECK: sdot v0.4s, v1.16b, v2.16b
>> +#CHECK: udot v0.2s, v1.8b, v2.4b[0]
>> +#CHECK: sdot v0.2s, v1.8b, v2.4b[1]
>> +#CHECK: udot v0.4s, v1.16b, v2.4b[2]
>> +#CHECK: sdot v0.4s, v1.16b, v2.4b[3]
>> +
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>> +# CHECK-ERROR: invalid instruction encoding
>>
>>
>> _______________________________________________
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>> llvm-commits at lists.llvm.org
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