[PATCH] D36601: [x86] Enable some support for lowerVectorShuffleWithUndefHalf with AVX-512

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 10 18:52:18 PDT 2017


craig.topper created this revision.

This teaches 512-bit shuffles to detect unused halfs in order to reduce shuffle size.

We may need to refine the 512-bit exit point. I couldn't remember if we had good cross lane shuffles for 8/16 bit with AVX-512 or not.

I believe this is step towards being able to handle https://reviews.llvm.org/D36454 without a special case.

>From here we need to improve our ability to combine extract_subvector with insert_subvector and other extract_subvectors. And we need to support narrowing binary operations where we don't demand all elements. This may be improvements to DAGCombiner::narrowExtractedVectorBinOp(by recognizing an insert_subvector in addition to concat) or we may need a target specific combiner.


https://reviews.llvm.org/D36601

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/sad.ll
  test/CodeGen/X86/vector-shuffle-512-v16.ll
  test/CodeGen/X86/vector-shuffle-512-v32.ll
  test/CodeGen/X86/vector-shuffle-512-v64.ll
  test/CodeGen/X86/vector-shuffle-512-v8.ll

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