[llvm] r310561 - [ARM][AArch64] ARMv8.3-A enablement
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 10 02:41:00 PDT 2017
Author: sam_parker
Date: Thu Aug 10 02:41:00 2017
New Revision: 310561
URL: http://llvm.org/viewvc/llvm-project?rev=310561&view=rev
Log:
[ARM][AArch64] ARMv8.3-A enablement
The beta ARMv8.3 ISA specifications have been released for AArch64
and AArch32, these can be found at:
https://developer.arm.com/products/architecture/a-profile/exploration-tools
An introduction to this architecture update can be found at:
https://community.arm.com/processors/b/blog/posts/armv8-a-architecture-2016-additions
This patch is the first in a series which will add ARM v8.3-A support
in LLVM and Clang. It adds the necessary changes that create targets
for both the ARM and AArch64 backends.
Differential Revision: https://reviews.llvm.org/D36514
Modified:
llvm/trunk/include/llvm/ADT/Triple.h
llvm/trunk/include/llvm/Support/AArch64TargetParser.def
llvm/trunk/include/llvm/Support/ARMTargetParser.def
llvm/trunk/lib/Support/TargetParser.cpp
llvm/trunk/lib/Support/Triple.cpp
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Thu Aug 10 02:41:00 2017
@@ -100,6 +100,7 @@ public:
enum SubArchType {
NoSubArch,
+ ARMSubArch_v8_3a,
ARMSubArch_v8_2a,
ARMSubArch_v8_1a,
ARMSubArch_v8,
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Thu Aug 10 02:41:00 2017
@@ -30,6 +30,10 @@ AARCH64_ARCH("armv8.2-a", ARMV8_2A, "8.2
(AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
AArch64::AEK_DOTPROD))
+AARCH64_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a",
+ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
+ (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
#undef AARCH64_ARCH
#ifndef AARCH64_ARCH_EXT_NAME
Modified: llvm/trunk/include/llvm/Support/ARMTargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ARMTargetParser.def?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ARMTargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/ARMTargetParser.def Thu Aug 10 02:41:00 2017
@@ -97,6 +97,10 @@ ARM_ARCH("armv8.2-a", ARMV8_2A, "8.2-A",
ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
(ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
+ARM_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a",
+ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
+ (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+ ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R,
FK_NEON_FP_ARMV8,
(ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
Modified: llvm/trunk/lib/Support/TargetParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/TargetParser.cpp?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Support/TargetParser.cpp (original)
+++ llvm/trunk/lib/Support/TargetParser.cpp Thu Aug 10 02:41:00 2017
@@ -463,6 +463,8 @@ bool llvm::AArch64::getArchFeatures(AArc
Features.push_back("+v8.1a");
if (AK == AArch64::ArchKind::ARMV8_2A)
Features.push_back("+v8.2a");
+ if (AK == AArch64::ArchKind::ARMV8_3A)
+ Features.push_back("+v8.3a");
return AK != AArch64::ArchKind::INVALID;
}
@@ -567,6 +569,7 @@ static StringRef getArchSynonym(StringRe
.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
.Case("v8.1a", "v8.1-a")
.Case("v8.2a", "v8.2-a")
+ .Case("v8.3a", "v8.3-a")
.Case("v8r", "v8-r")
.Case("v8m.base", "v8-m.base")
.Case("v8m.main", "v8-m.main")
@@ -719,6 +722,7 @@ ARM::ProfileKind ARM::parseArchProfile(S
case ARM::ArchKind::ARMV8A:
case ARM::ArchKind::ARMV8_1A:
case ARM::ArchKind::ARMV8_2A:
+ case ARM::ArchKind::ARMV8_3A:
return ARM::ProfileKind::A;
LLVM_FALLTHROUGH;
case ARM::ArchKind::ARMV2:
@@ -781,6 +785,7 @@ unsigned llvm::ARM::parseArchVersion(Str
case ARM::ArchKind::ARMV8A:
case ARM::ArchKind::ARMV8_1A:
case ARM::ArchKind::ARMV8_2A:
+ case ARM::ArchKind::ARMV8_3A:
case ARM::ArchKind::ARMV8R:
case ARM::ArchKind::ARMV8MBaseline:
case ARM::ArchKind::ARMV8MMainline:
Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Thu Aug 10 02:41:00 2017
@@ -581,6 +581,8 @@ static Triple::SubArchType parseSubArch(
return Triple::ARMSubArch_v8_1a;
case ARM::ArchKind::ARMV8_2A:
return Triple::ARMSubArch_v8_2a;
+ case ARM::ArchKind::ARMV8_3A:
+ return Triple::ARMSubArch_v8_3a;
case ARM::ArchKind::ARMV8R:
return Triple::ARMSubArch_v8r;
case ARM::ArchKind::ARMV8MBaseline:
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Aug 10 02:41:00 2017
@@ -146,6 +146,9 @@ def HasV8_1aOps : SubtargetFeature<"v8.1
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
"Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
+def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
+ "Support ARM v8.3a instructions", [HasV8_2aOps]>;
+
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Aug 10 02:41:00 2017
@@ -18,6 +18,8 @@ def HasV8_1a : Predicate<"Subtar
AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
+def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">,
+ AssemblerPredicate<"HasV8_3aOps", "armv8.3a">;
def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
def HasNEON : Predicate<"Subtarget->hasNEON()">,
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Aug 10 02:41:00 2017
@@ -58,6 +58,7 @@ protected:
bool HasV8_1aOps = false;
bool HasV8_2aOps = false;
+ bool HasV8_3aOps = false;
bool HasFPARMv8 = false;
bool HasNEON = false;
@@ -185,6 +186,7 @@ public:
bool hasV8_1aOps() const { return HasV8_1aOps; }
bool hasV8_2aOps() const { return HasV8_2aOps; }
+ bool hasV8_3aOps() const { return HasV8_3aOps; }
bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Thu Aug 10 02:41:00 2017
@@ -401,6 +401,9 @@ def HasV8_2aOps : SubtargetFeature<"v8.2
"Support ARM v8.2a instructions",
[HasV8_1aOps]>;
+def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
+ "Support ARM v8.3a instructions",
+ [HasV8_2aOps]>;
//===----------------------------------------------------------------------===//
// ARM Processor subtarget features.
@@ -578,6 +581,19 @@ def ARMv82a : Architecture<"armv8.2-a"
FeatureAClass,
FeatureDB,
FeatureFPARMv8,
+ FeatureNEON,
+ FeatureDSP,
+ FeatureTrustZone,
+ FeatureMP,
+ FeatureVirtualization,
+ FeatureCrypto,
+ FeatureCRC,
+ FeatureRAS]>;
+
+def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps,
+ FeatureAClass,
+ FeatureDB,
+ FeatureFPARMv8,
FeatureNEON,
FeatureDSP,
FeatureTrustZone,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 10 02:41:00 2017
@@ -241,6 +241,8 @@ def HasV8_1a : Predicate<"Subtar
AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
+def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">,
+ AssemblerPredicate<"HasV8_3aOps", "armv8.3a">;
def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
AssemblerPredicate<"FeatureVFP2", "VFP2">;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=310561&r1=310560&r2=310561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Aug 10 02:41:00 2017
@@ -98,6 +98,7 @@ protected:
ARMv7ve,
ARMv81a,
ARMv82a,
+ ARMv83a,
ARMv8a,
ARMv8mBaseline,
ARMv8mMainline,
@@ -143,6 +144,7 @@ protected:
bool HasV8Ops = false;
bool HasV8_1aOps = false;
bool HasV8_2aOps = false;
+ bool HasV8_3aOps = false;
bool HasV8MBaselineOps = false;
bool HasV8MMainlineOps = false;
@@ -492,6 +494,7 @@ public:
bool hasV8Ops() const { return HasV8Ops; }
bool hasV8_1aOps() const { return HasV8_1aOps; }
bool hasV8_2aOps() const { return HasV8_2aOps; }
+ bool hasV8_3aOps() const { return HasV8_3aOps; }
bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
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