[PATCH] D36571: [DAGCombiner] combine vextract (v1iX extract_subvector(vNiX, Idx)) into vextract(vNiX, Idx).
Elad Cohen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 10 01:54:41 PDT 2017
eladcohen created this revision.
Combine vextract (v1iX extract_subvector(vNiX, Idx)) into vextract(vNiX,Idx).
This case appeared in AVX512 after fixing pr33349 in r310552.
Usually we don't get these cases since v1iX are illegal in most targets and then these
(v1iX extract_subvector(vNiX, Idx)) get scalarized into (iX vextract(vNiX,Idx)).
But for targets like AVX512 where such type is legal we end up with a redundant DAG
node which can be combined.
https://reviews.llvm.org/D36571
Files:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/X86/pr33349.ll
Index: test/CodeGen/X86/pr33349.ll
===================================================================
--- test/CodeGen/X86/pr33349.ll
+++ test/CodeGen/X86/pr33349.ll
@@ -43,34 +43,26 @@
; SKX-NEXT: kshiftrw $2, %k0, %k1
; SKX-NEXT: kshiftlw $15, %k1, %k2
; SKX-NEXT: kshiftrw $15, %k2, %k2
-; SKX-NEXT: kshiftlw $15, %k2, %k2
-; SKX-NEXT: kshiftrw $15, %k2, %k2
; SKX-NEXT: kmovd %k2, %eax
; SKX-NEXT: testb $1, %al
; SKX-NEXT: fld1
; SKX-NEXT: fldz
; SKX-NEXT: fld %st(0)
; SKX-NEXT: fcmovne %st(2), %st(0)
; SKX-NEXT: kshiftlw $14, %k1, %k1
; SKX-NEXT: kshiftrw $15, %k1, %k1
-; SKX-NEXT: kshiftlw $15, %k1, %k1
-; SKX-NEXT: kshiftrw $15, %k1, %k1
; SKX-NEXT: kmovd %k1, %eax
; SKX-NEXT: testb $1, %al
; SKX-NEXT: fld %st(1)
; SKX-NEXT: fcmovne %st(3), %st(0)
; SKX-NEXT: kshiftlw $15, %k0, %k1
; SKX-NEXT: kshiftrw $15, %k1, %k1
-; SKX-NEXT: kshiftlw $15, %k1, %k1
-; SKX-NEXT: kshiftrw $15, %k1, %k1
; SKX-NEXT: kmovd %k1, %eax
; SKX-NEXT: testb $1, %al
; SKX-NEXT: fld %st(2)
; SKX-NEXT: fcmovne %st(4), %st(0)
; SKX-NEXT: kshiftlw $14, %k0, %k0
; SKX-NEXT: kshiftrw $15, %k0, %k0
-; SKX-NEXT: kshiftlw $15, %k0, %k0
-; SKX-NEXT: kshiftrw $15, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: testb $1, %al
; SKX-NEXT: fxch %st(3)
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13782,6 +13782,13 @@
// converts.
}
+ // vextract (v1iX extract_subvector(vNiX, Idx)) -> vextract(vNiX,Idx)
+ if (InVec.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
+ VT.getVectorNumElements() == 1) {
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
+ InVec->getOperand(0), InVec->getOperand(1));
+ }
+
// extract_vector_elt (v2i32 (bitcast i64:x)), EltTrunc -> i32 (trunc i64:x)
bool isLE = DAG.getDataLayout().isLittleEndian();
unsigned EltTrunc = isLE ? 0 : VT.getVectorNumElements() - 1;
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