[llvm] r310515 - AMDGPU: Fix assert on n inline asm constraint

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Aug  9 13:09:35 2017
New Revision: 310515

URL: http://llvm.org/viewvc/llvm-project?rev=310515&view=rev
Log:
AMDGPU: Fix assert on n inline asm constraint

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=310515&r1=310514&r2=310515&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Wed Aug  9 13:09:35 2017
@@ -1017,20 +1017,29 @@ void AMDGPUAsmPrinter::getAmdKernelCode(
 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                        unsigned AsmVariant,
                                        const char *ExtraCode, raw_ostream &O) {
+  // First try the generic code, which knows about modifiers like 'c' and 'n'.
+  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
+    return false;
+
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0)
       return true; // Unknown modifier.
 
     switch (ExtraCode[0]) {
-    default:
-      // See if this is a generic print operand
-      return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
     case 'r':
       break;
+    default:
+      return true;
     }
   }
 
-  AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
-                   *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
-  return false;
+  // TODO: Should be able to support other operand types like globals.
+  const MachineOperand &MO = MI->getOperand(OpNo);
+  if (MO.isReg()) {
+    AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
+                                       *MF->getSubtarget().getRegisterInfo());
+    return false;
+  }
+
+  return true;
 }

Modified: llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll?rev=310515&r1=310514&r2=310515&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll Wed Aug  9 13:09:35 2017
@@ -246,3 +246,19 @@ entry:
   store i32 %add, i32 addrspace(1)* undef
   ret void
 }
+
+; CHECK-LABEL: {{^}}asm_constraint_c_n:
+; CHECK: s_trap 10{{$}}
+define amdgpu_kernel void @asm_constraint_c_n()  {
+entry:
+  tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1
+  ret void
+}
+
+; CHECK-LABEL: {{^}}asm_constraint_n_n:
+; CHECK: s_trap -10{{$}}
+define amdgpu_kernel void @asm_constraint_n_n()  {
+entry:
+  tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
+  ret void
+}