[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection
Haicheng Wu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 9 12:30:10 PDT 2017
haicheng updated this revision to Diff 110454.
haicheng added a comment.
Fix a typo. Please take a look. Thank you.
Repository:
rL LLVM
https://reviews.llvm.org/D36104
Files:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
test/CodeGen/AArch64/arm64-addr-type-promotion.ll
test/CodeGen/AArch64/arm64-cse.ll
test/CodeGen/AArch64/copy-zero-reg.ll
test/CodeGen/AArch64/i128-fast-isel-fallback.ll
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