[PATCH] D36511: [SelectionDAG] When scalarizing vselect, don't assert on a legal cond operand.
Elad Cohen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 9 08:07:09 PDT 2017
eladcohen marked an inline comment as done.
eladcohen added a comment.
In https://reviews.llvm.org/D36511#836697, @RKSimon wrote:
> LGTM, with one minor.
>
> PS - nothing to do with this patch but those mask vector shifts are awful.
Thanks for the review!
About the shifts - in the test we can see redundant shifts (due to "extract_elt (extract_subvector X)" ) :
; SKX-NEXT: kshiftlw $15, %k0, %k1
; SKX-NEXT: kshiftrw $15, %k1, %k1
; SKX-NEXT: kshiftlw $15, %k1, %k1
; SKX-NEXT: kshiftrw $15, %k1, %k1
I'm going to upload a dag combine for
vextract (v1iX extract_subvector(vNiX, Idx)) -> vextract(vNiX,Idx)
which will eliminate the redundant shifts.
About the usage of shifts for extracting the bit in general we have: https://bugs.llvm.org/show_bug.cgi?id=33692 - so that's at least one way we can improve this I guess.
https://reviews.llvm.org/D36511
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