[PATCH] D36396: [AArch64] Do not promote f16 when subtarget HasFullFP16

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added a comment.

I think we could still do with tests for how half-precision constants are code-generated from IR (using FMOV or constant pools). I don't see any existing tests for that.

There are also a few classes of instruction where we still promote to 32-bit float, but it looks like we have the instructions to do them directly in half-precision. If they turn out to be more complicated that changing a setOperationAction call, then it would make sense to do them as separate patches though.



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Comment at: test/CodeGen/AArch64/f16-instructions.ll:517
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: fcvtzs w0, s0
+; CHECK-COMMON-NEXT: ret
----------------
Could this be selected as "fcvtzs w0, h0"?


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Comment at: test/CodeGen/AArch64/f16-instructions.ll:903
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: movi.4s v2, #128, lsl #24
+; CHECK-COMMON-NEXT: bit.16b v0, v1, v2
----------------
Could this be done without the FCVTs, by changing the constant?


https://reviews.llvm.org/D36396