[PATCH] D35761: [Polly][WIP] Use SCEV information for the second level aliasing

[Roman via Phabricator via llvm-commits]

gareevroman added a comment.

In https://reviews.llvm.org/D35761#833110, @grosser wrote:

> OK, that's fine for me than. Can you possibly add to the test case check lines for the load and store to illustrate to which alias data they refer to?


AFAIU, it'd require to add IR and make it dependent on the generated code. I'm not sure that it's a good approach.


Repository:
  rL LLVM

https://reviews.llvm.org/D35761