[llvm] r310243 - [ARM] Fix assembly and disassembly for VMRS/VMSR

Andre Simoes Dias Vieira via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 8 09:45:36 PDT 2017

Hi Tim,

Oh bummer... I knew I should've looked harder for those fpinst ones, I
might have found the others.

I am about to go on holidays though, I will have another go at it when
I'm back in a week.


On 08/08/17 17:18, Tim Northover wrote:
> Hi Andre,
> On 7 August 2017 at 01:41, Andre Vieira via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>> 1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
>>   accepted for non ARMv8-A targets.
> I now think this was too aggressive. When I looked at the patch
> originally I didn't notice anything in the manual about using these
> registers on v7 but I had a closer look after one of our internal
> tests failed.
> It turns out I wan't looking hard enough, and the VMRS/VMSR have
> another definition in the system instructions section (B9.3.21 &
> B9.3.22 of the v7-AR ARM ARM). These bless fpsid, mvfr0, mvfr1 and
> fpexc. D6.6.3 also seems to allow the fpinst instructions, thought
> they're omitted from the instruction definitions (probably a bug).
> So I think the only one that's really not allowed except on v8 is
> mvfr2. Could you take a look and fix the situation?
> Cheers.
> Tim.

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