[llvm] r310372 - [DAGCombiner] simplifyShuffleMask - handle UNDEF inputs from shuffles as well as BUILD_VECTOR
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 8 09:10:33 PDT 2017
Author: rksimon
Date: Tue Aug 8 09:10:33 2017
New Revision: 310372
URL: http://llvm.org/viewvc/llvm-project?rev=310372&view=rev
Log:
[DAGCombiner] simplifyShuffleMask - handle UNDEF inputs from shuffles as well as BUILD_VECTOR
Minor extension to D36393
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/oddshuffles.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=310372&r1=310371&r2=310372&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Aug 8 09:10:33 2017
@@ -15114,11 +15114,14 @@ static SDValue simplifyShuffleOperands(S
static SDValue simplifyShuffleMask(ShuffleVectorSDNode *SVN, SDValue N0,
SDValue N1, SelectionDAG &DAG) {
- // TODO - handle cases other than BUILD_VECTOR.
- auto *BV0 = dyn_cast<BuildVectorSDNode>(N0);
- auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
- if (!BV0 && !BV1)
- return SDValue();
+ auto isUndefElt = [](SDValue V, int Idx) {
+ // TODO - handle more cases as required.
+ if (V.getOpcode() == ISD::BUILD_VECTOR)
+ return V.getOperand(Idx).isUndef();
+ if (auto *SVN = dyn_cast<ShuffleVectorSDNode>(V))
+ return SVN->getMaskElt(Idx) < 0;
+ return false;
+ };
EVT VT = SVN->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();
@@ -15127,12 +15130,8 @@ static SDValue simplifyShuffleMask(Shuff
SmallVector<int, 8> NewMask;
for (unsigned i = 0; i != NumElts; ++i) {
int Idx = SVN->getMaskElt(i);
- if (BV0 && 0 <= Idx && Idx < (int)NumElts &&
- BV0->getOperand(Idx).isUndef()) {
- Changed = true;
- Idx = -1;
- } else if (BV1 && Idx > (int)NumElts &&
- BV1->getOperand(Idx - NumElts).isUndef()) {
+ if ((0 <= Idx && Idx < (int)NumElts && isUndefElt(N0, Idx)) ||
+ ((int)NumElts < Idx && isUndefElt(N1, Idx - NumElts))) {
Changed = true;
Idx = -1;
}
Modified: llvm/trunk/test/CodeGen/X86/oddshuffles.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/oddshuffles.ll?rev=310372&r1=310371&r2=310372&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/oddshuffles.ll (original)
+++ llvm/trunk/test/CodeGen/X86/oddshuffles.ll Tue Aug 8 09:10:33 2017
@@ -258,7 +258,7 @@ define void @v7i8(<4 x i8> %a, <4 x i8>
; SSE42-NEXT: pextrb $0, %xmm1, 6(%rdi)
; SSE42-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8,9,8,9,4,5,8,9,0,1,12,13,0,1,14,15]
; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5,6,7]
-; SSE42-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; SSE42-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,2,4,6,8,10,12,u,u,u,u,u,u,u,u,u]
; SSE42-NEXT: pextrw $2, %xmm1, 4(%rdi)
; SSE42-NEXT: movd %xmm1, (%rdi)
; SSE42-NEXT: retq
@@ -268,7 +268,7 @@ define void @v7i8(<4 x i8> %a, <4 x i8>
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,3,1,3]
; AVX-NEXT: vpshufb {{.*#+}} xmm2 = xmm1[8,9,8,9,4,5,8,9,0,1,12,13,0,1,14,15]
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5,6,7]
-; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
+; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,u,u,u,u,u,u,u,u,u]
; AVX-NEXT: vpextrb $0, %xmm1, 6(%rdi)
; AVX-NEXT: vpextrw $2, %xmm0, 4(%rdi)
; AVX-NEXT: vmovd %xmm0, (%rdi)
More information about the llvm-commits
mailing list