[llvm] r310337 - AMDGPU: Fix warnings introduced by r310336

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Mon Aug  7 22:52:00 2017
New Revision: 310337

URL: http://llvm.org/viewvc/llvm-project?rev=310337&view=rev
Log:
AMDGPU: Fix warnings introduced by r310336

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp?rev=310337&r1=310336&r2=310337&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp Mon Aug  7 22:52:00 2017
@@ -383,7 +383,6 @@ static bool getConstantValue(SDValue N,
 }
 
 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
-  unsigned Opc = N->getOpcode();
   EVT VT = N->getValueType(0);
   unsigned NumVectorElts = VT.getVectorNumElements();
   EVT EltVT = VT.getVectorElementType();
@@ -420,7 +419,7 @@ void AMDGPUDAGToDAGISel::SelectBuildVect
   }
   if (NOps != NumVectorElts) {
     // Fill in the missing undef elements if this was a scalar_to_vector.
-    assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
+    assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
     MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
                                                    DL, EltVT);
     for (unsigned i = NOps; i < NumVectorElts; ++i) {
@@ -481,7 +480,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *
   case ISD::BUILD_VECTOR: {
     EVT VT = N->getValueType(0);
     unsigned NumVectorElts = VT.getVectorNumElements();
-    EVT EltVT = VT.getVectorElementType();
 
     if (VT == MVT::v2i16 || VT == MVT::v2f16) {
       if (Opc == ISD::BUILD_VECTOR) {
@@ -498,7 +496,7 @@ void AMDGPUDAGToDAGISel::Select(SDNode *
       break;
     }
 
-    assert(EltVT.bitsEq(MVT::i32));
+    assert(VT.getVectorElementType().bitsEq(MVT::i32));
     unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
     SelectBuildVector(N, RegClassID);
     return;