[llvm] r310310 - AMDGPU: Implement getMinimumNopSize

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 7 15:00:58 PDT 2017


Author: arsenm
Date: Mon Aug  7 15:00:58 2017
New Revision: 310310

URL: http://llvm.org/viewvc/llvm-project?rev=310310&view=rev
Log:
AMDGPU: Implement getMinimumNopSize

Modified:
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=310310&r1=310309&r2=310310&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Mon Aug  7 15:00:58 2017
@@ -43,6 +43,8 @@ public:
     llvm_unreachable("Not implemented");
   }
   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
+
+  unsigned getMinimumNopSize() const override;
   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
@@ -133,6 +135,10 @@ const MCFixupKindInfo &AMDGPUAsmBackend:
   return Infos[Kind - FirstTargetFixupKind];
 }
 
+unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
+  return 4;
+}
+
 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far




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