[llvm] r310251 - [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 7 06:14:13 PDT 2017
Author: dpreobra
Date: Mon Aug 7 06:14:12 2017
New Revision: 310251
URL: http://llvm.org/viewvc/llvm-project?rev=310251&view=rev
Log:
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35902
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
llvm/trunk/test/MC/AMDGPU/vop3-errs.s
llvm/trunk/test/MC/AMDGPU/vop3.s
llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Aug 7 06:14:12 2017
@@ -164,7 +164,8 @@ public:
ImmTyOpSelHi,
ImmTyNegLo,
ImmTyNegHi,
- ImmTySwizzle
+ ImmTySwizzle,
+ ImmTyHigh
};
struct TokOp {
@@ -312,6 +313,7 @@ public:
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
bool isNegHi() const { return isImmTy(ImmTyNegHi); }
+ bool isHigh() const { return isImmTy(ImmTyHigh); }
bool isMod() const {
return isClampSI() || isOModSI();
@@ -673,6 +675,7 @@ public:
case ImmTyNegLo: OS << "NegLo"; break;
case ImmTyNegHi: OS << "NegHi"; break;
case ImmTySwizzle: OS << "Swizzle"; break;
+ case ImmTyHigh: OS << "High"; break;
}
}
@@ -1064,6 +1067,8 @@ public:
void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
+ void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
+
void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
bool IsAtomic = false);
void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
@@ -4020,6 +4025,7 @@ static const OptionalOperand AMDGPUOptio
{"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
{"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
{"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
+ {"high", AMDGPUOperand::ImmTyHigh, true, nullptr},
{"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
{"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
{"unorm", AMDGPUOperand::ImmTyUNorm, true, nullptr},
@@ -4122,6 +4128,45 @@ static bool isRegOrImmWithInputMods(cons
&& Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
}
+void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) {
+
+ OptionalImmIndexMap OptionalIdx;
+ unsigned Opc = Inst.getOpcode();
+
+ unsigned I = 1;
+ const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
+ for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
+ ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
+ }
+
+ for (unsigned E = Operands.size(); I != E; ++I) {
+ AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
+ if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
+ Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
+ } else if (Op.isInterpSlot() ||
+ Op.isInterpAttr() ||
+ Op.isAttrChan()) {
+ Inst.addOperand(MCOperand::createImm(Op.Imm.Val));
+ } else if (Op.isImmModifier()) {
+ OptionalIdx[Op.getImmTy()] = I;
+ } else {
+ llvm_unreachable("unhandled operand type");
+ }
+ }
+
+ if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) {
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);
+ }
+
+ if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
+ }
+
+ if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
+ }
+}
+
void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
OptionalImmIndexMap &OptionalIdx) {
unsigned Opc = Inst.getOpcode();
Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Mon Aug 7 06:14:12 2017
@@ -981,6 +981,13 @@ void AMDGPUInstPrinter::printClamp(const
printIfSet(MI, OpNo, O, "_SAT");
}
+void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNo).getImm())
+ O << " high";
+}
+
void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h Mon Aug 7 06:14:12 2017
@@ -170,6 +170,8 @@ private:
char Asm);
void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
+ void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon Aug 7 06:14:12 2017
@@ -556,6 +556,7 @@ def gds : NamedOperandBit<"GDS", NamedMa
def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
+def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
@@ -1511,6 +1512,7 @@ class VOPProfile <list<ValueType> _ArgVT
field bit HasClamp = HasModifiers;
field bit HasSDWAClamp = EmitDst;
field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
+ field bit HasHigh = 0;
field bit IsPacked = isPackedType<Src0VT>.ret;
field bit HasOpSel = IsPacked;
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Mon Aug 7 06:14:12 2017
@@ -175,6 +175,68 @@ def VOP3b_I64_I1_I32_I32_I64 : VOPProfil
}
//===----------------------------------------------------------------------===//
+// VOP3 INTERP
+//===----------------------------------------------------------------------===//
+
+class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
+ let AsmMatchConverter = "cvtVOP3Interp";
+}
+
+def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
+ let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+ Attr:$attr, AttrChan:$attrchan,
+ clampmod:$clamp, omod:$omod);
+
+ let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
+}
+
+def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
+ let Ins64 = (ins InterpSlot:$src0,
+ Attr:$attr, AttrChan:$attrchan,
+ clampmod:$clamp, omod:$omod);
+
+ let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
+
+ let HasClamp = 1;
+}
+
+class getInterp16Asm <bit HasSrc2, bit HasOMod> {
+ string src2 = !if(HasSrc2, ", $src2_modifiers", "");
+ string omod = !if(HasOMod, "$omod", "");
+ string ret =
+ " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
+}
+
+class getInterp16Ins <bit HasSrc2, bit HasOMod,
+ Operand Src0Mod, Operand Src2Mod> {
+ dag ret = !if(HasSrc2,
+ !if(HasOMod,
+ (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+ Attr:$attr, AttrChan:$attrchan,
+ Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+ highmod:$high, clampmod:$clamp, omod:$omod),
+ (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+ Attr:$attr, AttrChan:$attrchan,
+ Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+ highmod:$high, clampmod:$clamp)
+ ),
+ (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
+ Attr:$attr, AttrChan:$attrchan,
+ highmod:$high, clampmod:$clamp, omod:$omod)
+ );
+}
+
+class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
+
+ let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
+ let HasHigh = 1;
+
+ let Outs64 = (outs VGPR_32:$vdst);
+ let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
+ let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
+}
+
+//===----------------------------------------------------------------------===//
// VOP3 Instructions
//===----------------------------------------------------------------------===//
@@ -315,9 +377,11 @@ def V_DIV_FIXUP_F16 : VOP3Inst <"v_div
let isCommutable = 1 in {
def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
-def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>;
-def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>;
-def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>;
+
+def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
+def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
+def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
+
def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
@@ -327,6 +391,10 @@ def V_MAD_I16 : VOP3Inst <"v_mad_i16", V
} // End SubtargetPredicate = Has16BitInsts
let SubtargetPredicate = isVI in {
+def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
+def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
+def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
+
def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
} // End SubtargetPredicate = isVI
@@ -512,6 +580,11 @@ multiclass VOP3OpSel_Real_gfx9<bits<10>
VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
+multiclass VOP3Interp_Real_vi<bits<10> op> {
+ def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
+ VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
+}
+
} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
@@ -567,9 +640,13 @@ defm V_PERM_B32 : VOP3_Real_vi <
defm V_FMA_F16 : VOP3_Real_vi <0x1ee>;
defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>;
-defm V_INTERP_P1LL_F16 : VOP3_Real_vi <0x274>;
-defm V_INTERP_P1LV_F16 : VOP3_Real_vi <0x275>;
-defm V_INTERP_P2_F16 : VOP3_Real_vi <0x276>;
+defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
+defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
+defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
+
+defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
+defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
+defm V_INTERP_P2_F16 : VOP3Interp_Real_vi <0x276>;
defm V_ADD_F64 : VOP3_Real_vi <0x280>;
defm V_MUL_F64 : VOP3_Real_vi <0x281>;
defm V_MIN_F64 : VOP3_Real_vi <0x282>;
Modified: llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td Mon Aug 7 06:14:12 2017
@@ -204,6 +204,25 @@ class VOP3OpSel_gfx9 <bits<10> op, VOPPr
let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
}
+// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
+class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
+ bits<2> attrchan;
+ bits<6> attr;
+ bits<1> high;
+
+ let Inst{8} = 0; // No modifiers for src0
+ let Inst{61} = 0;
+
+ let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
+ let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
+
+ let Inst{37-32} = attr;
+ let Inst{39-38} = attrchan;
+ let Inst{40} = !if(P.HasHigh, high, 0);
+
+ let Inst{49-41} = src0;
+}
+
class VOP3be <VOPProfile P> : Enc64 {
bits<8> vdst;
bits<2> src0_modifiers;
Modified: llvm/trunk/test/MC/AMDGPU/vop3-errs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3-errs.s?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3-errs.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop3-errs.s Mon Aug 7 06:14:12 2017
@@ -44,4 +44,36 @@ v_cmp_le_f64_e64 vcc, v0, v1 mul:4
// GCN: error: invalid operand for instruction
v_cvt_u32_f32_e64 v0, v1 div:2
-// GCN: error: invalid operand for instruction
\ No newline at end of file
+// GCN: error: invalid operand for instruction
+
+//
+// v_interp*
+//
+
+v_interp_mov_f32_e64 v5, p10, attr0.x high
+// GCN: error: invalid operand for instruction
+
+v_interp_mov_f32_e64 v5, p10, attr0.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p1_f32_e64 v5, v2, attr0.x high
+// GCN: error: invalid operand for instruction
+
+v_interp_p1_f32_e64 v5, v2, attr0.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p2_f32_e64 v255, v2, attr0.x high
+// GCN: error: invalid operand for instruction
+
+v_interp_p2_f32_e64 v255, v2, attr0.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p1ll_f16 v5, p0, attr31.x
+// GCN: error: invalid operand for instruction
+
+v_interp_p1ll_f16 v5, v2, attr31.x v0
+// GCN: error: invalid operand for instruction
+
+v_interp_p2_f16 v5, v2, attr1.x, v3 mul:2
+// GFX67: error: not a valid operand
+// GFX89: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/AMDGPU/vop3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3.s?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop3.s Mon Aug 7 06:14:12 2017
@@ -435,3 +435,208 @@ v_mul_f64 v[0:1], |0|, |0|
v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
// SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
// VI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
+
+//
+// v_interp*
+//
+
+v_interp_mov_f32_e64 v5, p10, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr32.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p20, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.w
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32 v5, p10, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+
+v_interp_mov_f32 v5, p10, attr0.x div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+
+
+v_interp_p1_f32_e64 v5, v2, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.y
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, -v2, attr0.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1_f32_e64 v5, |v2|, attr0.x
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
+
+
+v_interp_p2_f32_e64 v255, v2, attr0.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr31.x
+// NOSICI: error: instruction not supported on this GPU
+// VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, -v2, attr0.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p2_f32_e64 v5, |v2|, attr0.x
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
+
+
+v_interp_p1ll_f16 v5, v2, attr31.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr31.x ; encoding: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.w
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr0.w ; encoding: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, -v2, attr0.x
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1ll_f16 v5, |v2|, attr0.x
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x high
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:4
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1ll_f16 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
+
+
+v_interp_p1lv_f16 v5, v2, attr1.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.z, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.z, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, -v2, attr0.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, -v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
+// NOSICI: error: not a valid operand
+// VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
+
+
+v_interp_p2_f16 v5, v2, attr1.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr32.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.w, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, -v2, attr0.x, v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_f16 v5, v2, attr0.x, -v3
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p2_f16 v5, |v2|, attr0.x, v3
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, |v3|
+// NOSICI: error: not a valid operand
+// VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 high
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
+// NOSICI: error: invalid operand for instruction
+// VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt?rev=310251&r1=310250&r2=310251&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt Mon Aug 7 06:14:12 2017
@@ -239,3 +239,144 @@
# VI: v_ceil_f32_e64 v0, neg(-1.0) ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
+0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
+0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10
+
+# VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18
+
+# VI: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
+0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
+0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40
+
+# VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
+0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
+0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
+0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
+0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40
+
+# VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
+0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
+0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr1.x ; encoding: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
+0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40
+
+# VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.y ; encoding: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
+0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
+0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00
+
+# VI: v_interp_p1ll_f16 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
+0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18
+
+# VI: v_interp_p1lv_f16 v255, v2, attr0.x, v3 ; encoding: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
+0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
+0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
+0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84
+
+# VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
+0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
+0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
+0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84
+
+# VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
+
+# VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
+0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04
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