[llvm] r309990 - [GlobalISel] Make GlobalISel a non-optional library.
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 7 01:34:26 PDT 2017
On 4 August 2017 at 18:15, Quentin Colombet <qcolombet at apple.com> wrote:
> Hi Diane,
>
> Thanks for the feedbacks.
>
> On Aug 4, 2017, at 1:25 AM, Diana Picus <diana.picus at linaro.org> wrote:
>
> Just a few nits:
>
> On 3 August 2017 at 23:52, Quentin Colombet via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>
> Author: qcolombet
> Date: Thu Aug 3 14:52:25 2017
> New Revision: 309990
>
> URL: http://llvm.org/viewvc/llvm-project?rev=309990&view=rev
> Log:
> [GlobalISel] Make GlobalISel a non-optional library.
>
> With this change, the GlobalISel library gets always built. In
> particular, this is not possible to opt GlobalISel out of the build
> using the LLVM_BUILD_GLOBAL_ISEL variable any more.
>
> Modified:
> llvm/trunk/CMakeLists.txt
> llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt
> llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp
> llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
> llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
> llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> llvm/trunk/lib/Target/AArch64/CMakeLists.txt
> llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
> llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
> llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
> llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt
> llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
> llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/lib/Target/ARM/CMakeLists.txt
> llvm/trunk/lib/Target/X86/CMakeLists.txt
> llvm/trunk/lib/Target/X86/X86CallLowering.cpp
> llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def
> llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
> llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
> llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
> llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> llvm/trunk/tools/llvm-config/CMakeLists.txt
> llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt
>
> Modified: llvm/trunk/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/CMakeLists.txt (original)
> +++ llvm/trunk/CMakeLists.txt Thu Aug 3 14:52:25 2017
> @@ -176,11 +176,6 @@ if(LLVM_DEPENDENCY_DEBUGGING)
> endif()
> endif()
>
> -option(LLVM_BUILD_GLOBAL_ISEL "Experimental: Build GlobalISel" ON)
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - add_definitions(-DLLVM_BUILD_GLOBAL_ISEL)
> -endif()
> -
> option(LLVM_ENABLE_DAGISEL_COV "Debug: Prints tablegen patterns that were
> used for selecting" OFF)
>
> # Add path for custom modules
>
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/CMakeLists.txt Thu Aug 3 14:52:25
> 2017
> @@ -1,34 +1,21 @@
> -# List of all GlobalISel files.
> -set(GLOBAL_ISEL_FILES
> - CallLowering.cpp
> - IRTranslator.cpp
> - InstructionSelect.cpp
> - InstructionSelector.cpp
> - MachineIRBuilder.cpp
> - LegalizerHelper.cpp
> - Legalizer.cpp
> - LegalizerInfo.cpp
> - Localizer.cpp
> - RegBankSelect.cpp
> - RegisterBank.cpp
> - RegisterBankInfo.cpp
> - Utils.cpp
> - )
> -
> -# Add GlobalISel files to the dependencies if the user wants to build it.
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
> -else()
> - set(GLOBAL_ISEL_BUILD_FILES"")
> - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
> -endif()
> -
> # In LLVMBuild.txt files, it is not possible to mark a dependency to a
> # library as optional. So instead, generate an empty library if we did
> # not ask for it.
>
>
> This comment doesn't seem necessary anymore.
>
>
>
> Good point.
>
>
> add_llvm_library(LLVMGlobalISel
> - ${GLOBAL_ISEL_BUILD_FILES}
> + CallLowering.cpp
> GlobalISel.cpp
> + IRTranslator.cpp
> + InstructionSelect.cpp
> + InstructionSelector.cpp
> + LegalizerHelper.cpp
> + Legalizer.cpp
> + LegalizerInfo.cpp
> + Localizer.cpp
> + MachineIRBuilder.cpp
> + RegBankSelect.cpp
> + RegisterBank.cpp
> + RegisterBankInfo.cpp
> + Utils.cpp
>
> DEPENDS
> intrinsics_gen
>
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/GlobalISel.cpp Thu Aug 3 14:52:25
> 2017
> @@ -16,13 +16,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -
> -void llvm::initializeGlobalISel(PassRegistry &Registry) {
> -}
> -
> -#else
> -
> void llvm::initializeGlobalISel(PassRegistry &Registry) {
> initializeIRTranslatorPass(Registry);
> initializeLegalizerPass(Registry);
> @@ -30,4 +23,3 @@ void llvm::initializeGlobalISel(PassRegi
> initializeRegBankSelectPass(Registry);
> initializeInstructionSelectPass(Registry);
> }
> -#endif // LLVM_BUILD_GLOBAL_ISEL
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp Thu Aug 3
> 14:52:25 2017
> @@ -47,10 +47,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "This shouldn't be built without GISel"
> -#endif
> -
> AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
> : CallLowering(&TLI) {}
>
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def Thu Aug 3
> 14:52:25 2017
> @@ -11,10 +11,6 @@
> /// \todo This should be generated by TableGen.
> //===----------------------------------------------------------------------===//
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> namespace llvm {
> RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
> /* StartIdx, Length, RegBank */
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Aug 3
> 14:52:25 2017
> @@ -37,10 +37,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> namespace {
>
> #define GET_GLOBALISEL_PREDICATE_BITSET
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Aug 3
> 14:52:25 2017
> @@ -23,10 +23,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> AArch64LegalizerInfo::AArch64LegalizerInfo() {
> using namespace TargetOpcode;
> const LLT p0 = LLT::pointer(0, 64);
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Aug 3
> 14:52:25 2017
> @@ -37,10 +37,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo
> &TRI)
> : AArch64GenRegisterBankInfo() {
> static bool AlreadyInit = false;
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Thu Aug 3 14:52:25
> 2017
> @@ -18,7 +18,6 @@
> #include "AArch64PBQPRegAlloc.h"
> #include "AArch64TargetMachine.h"
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> #include "AArch64CallLowering.h"
> #include "AArch64LegalizerInfo.h"
> #include "AArch64RegisterBankInfo.h"
> @@ -27,7 +26,6 @@
> #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
> #include "llvm/CodeGen/GlobalISel/Legalizer.h"
> #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
> -#endif
> #include "llvm/CodeGen/MachineScheduler.h"
> #include "llvm/IR/GlobalValue.h"
> #include "llvm/Support/TargetRegistry.h"
>
>
> Maybe sort the includes?
>
>
> I’ve run clang-format and didn’t check afterward, I though it was supposed
> to do this kind of thing.
> That being said, a quick glance at this part of the diff seems to be fine
> (GlobalISel is before MachineScheduler).
> Am I missing something?
Hm, I think I had in mind the AArch64* includes (PBQPRegAlloc comes
before CallLowering). I guess clang-format didn't touch them because
they're separated from the others with a newline. Doesn't look like a
very relevant separation though...
>
> @@ -143,7 +141,6 @@ void AArch64Subtarget::initializePropert
> }
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> namespace {
>
> struct AArch64GISelActualAccessor : public GISelAccessor {
>
>
> I suppose now we don't need to call it "actual" anymore, right?
>
>
> Indeed. I suppose we could get rid of the GISelAccessor thing all together.
> What do you think?
>
> Cheers,
> -Quentin
>
>
> @@ -170,7 +167,6 @@ struct AArch64GISelActualAccessor : publ
> };
>
> } // end anonymous namespace
> -#endif
>
> AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
> const std::string &FS,
> @@ -180,9 +176,6 @@ AArch64Subtarget::AArch64Subtarget(const
> IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(),
> InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
> TLInfo(TM, *this), GISel() {
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> - GISelAccessor *AArch64GISel = new GISelAccessor();
> -#else
> AArch64GISelActualAccessor *AArch64GISel = new
> AArch64GISelActualAccessor();
> AArch64GISel->CallLoweringInfo.reset(
> new AArch64CallLowering(*getTargetLowering()));
> @@ -197,7 +190,6 @@ AArch64Subtarget::AArch64Subtarget(const
> *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
>
> AArch64GISel->RegBankInfo.reset(RBI);
> -#endif
> setGISelAccessor(*AArch64GISel);
> }
>
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Aug 3
> 14:52:25 2017
> @@ -330,13 +330,11 @@ public:
> void addIRPasses() override;
> bool addPreISel() override;
> bool addInstSelector() override;
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool addIRTranslator() override;
> bool addLegalizeMachineIR() override;
> bool addRegBankSelect() override;
> void addPreGlobalInstructionSelect() override;
> bool addGlobalInstructionSelect() override;
> -#endif
> bool addILPOpts() override;
> void addPreRegAlloc() override;
> void addPostRegAlloc() override;
> @@ -432,7 +430,6 @@ bool AArch64PassConfig::addInstSelector(
> return false;
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool AArch64PassConfig::addIRTranslator() {
> addPass(new IRTranslator());
> return false;
> @@ -458,7 +455,6 @@ bool AArch64PassConfig::addGlobalInstruc
> addPass(new InstructionSelect());
> return false;
> }
> -#endif
>
> bool AArch64PassConfig::isGlobalISelEnabled() const {
> return TM->getOptLevel() <= EnableGlobalISelAtO;
>
> Modified: llvm/trunk/lib/Target/AArch64/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/AArch64/CMakeLists.txt Thu Aug 3 14:52:25 2017
> @@ -13,34 +13,16 @@ tablegen(LLVM AArch64GenCallingConv.inc
> tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
> tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
> tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
> - tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
> -endif()
> +tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
> +tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
>
> add_public_tablegen_target(AArch64CommonTableGen)
>
> -# List of all GlobalISel files.
> -set(GLOBAL_ISEL_FILES
> - AArch64CallLowering.cpp
> - AArch64InstructionSelector.cpp
> - AArch64LegalizerInfo.cpp
> - AArch64RegisterBankInfo.cpp
> - )
> -
> -# Add GlobalISel files to the dependencies if the user wants to build it.
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
> -else()
> - set(GLOBAL_ISEL_BUILD_FILES"")
> - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
> -endif()
> -
> -
> add_llvm_target(AArch64CodeGen
> AArch64A57FPLoadBalancing.cpp
> AArch64AdvSIMDScalarPass.cpp
> AArch64AsmPrinter.cpp
> + AArch64CallLowering.cpp
> AArch64CleanupLocalDynamicTLSPass.cpp
> AArch64CollectLOH.cpp
> AArch64CondBrTuning.cpp
> @@ -56,11 +38,14 @@ add_llvm_target(AArch64CodeGen
> AArch64ISelDAGToDAG.cpp
> AArch64ISelLowering.cpp
> AArch64InstrInfo.cpp
> + AArch64InstructionSelector.cpp
> + AArch64LegalizerInfo.cpp
> AArch64LoadStoreOptimizer.cpp
> AArch64MacroFusion.cpp
> AArch64MCInstLower.cpp
> AArch64PromoteConstant.cpp
> AArch64PBQPRegAlloc.cpp
> + AArch64RegisterBankInfo.cpp
> AArch64RegisterInfo.cpp
> AArch64SelectionDAGInfo.cpp
> AArch64StorePairSuppress.cpp
> @@ -69,7 +54,6 @@ add_llvm_target(AArch64CodeGen
> AArch64TargetObjectFile.cpp
> AArch64TargetTransformInfo.cpp
> AArch64VectorByElementOpt.cpp
> - ${GLOBAL_ISEL_BUILD_FILES}
>
> DEPENDS
> intrinsics_gen
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp Thu Aug 3 14:52:25
> 2017
> @@ -26,10 +26,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "This shouldn't be built without GISel"
> -#endif
> -
> AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
> : CallLowering(&TLI), AMDGPUASI(TLI.getAMDGPUAS()) {
> }
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def Thu Aug 3
> 14:52:25 2017
> @@ -11,10 +11,6 @@
> /// \todo This should be generated by TableGen.
> //===----------------------------------------------------------------------===//
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> namespace llvm {
> namespace AMDGPU {
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Aug 3 14:52:25
> 2017
> @@ -21,10 +21,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
> using namespace TargetOpcode;
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Thu Aug 3
> 14:52:25 2017
> @@ -29,10 +29,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo
> &TRI)
> : AMDGPUGenRegisterBankInfo(),
> TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Thu Aug 3 14:52:25
> 2017
> @@ -15,12 +15,10 @@
> #include "AMDGPUSubtarget.h"
> #include "AMDGPU.h"
> #include "AMDGPUTargetMachine.h"
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> #include "AMDGPUCallLowering.h"
> #include "AMDGPUInstructionSelector.h"
> #include "AMDGPULegalizerInfo.h"
> #include "AMDGPURegisterBankInfo.h"
> -#endif
> #include "SIMachineFunctionInfo.h"
> #include "llvm/ADT/SmallString.h"
> #include "llvm/CodeGen/MachineScheduler.h"
> @@ -80,7 +78,6 @@ AMDGPUSubtarget::initializeSubtargetDepe
> return *this;
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> namespace {
>
> struct SIGISelActualAccessor : public GISelAccessor {
> @@ -103,7 +100,6 @@ struct SIGISelActualAccessor : public GI
> };
>
> } // end anonymous namespace
> -#endif
>
> AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef
> FS,
> const TargetMachine &TM)
> @@ -358,9 +354,6 @@ SISubtarget::SISubtarget(const Triple &T
> : AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this),
> FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(),
> 0),
> TLInfo(TM, *this) {
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> - GISelAccessor *GISel = new GISelAccessor();
> -#else
> SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
> GISel->CallLoweringInfo.reset(new
> AMDGPUCallLowering(*getTargetLowering()));
> GISel->Legalizer.reset(new AMDGPULegalizerInfo());
> @@ -368,7 +361,6 @@ SISubtarget::SISubtarget(const Triple &T
> GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo()));
> GISel->InstSelector.reset(new AMDGPUInstructionSelector(
> *this, *static_cast<AMDGPURegisterBankInfo
> *>(GISel->RegBankInfo.get())));
> -#endif
> setGISelAccessor(*GISel);
> }
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Thu Aug 3 14:52:25
> 2017
> @@ -516,12 +516,10 @@ public:
> void addMachineSSAOptimization() override;
> bool addILPOpts() override;
> bool addInstSelector() override;
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool addIRTranslator() override;
> bool addLegalizeMachineIR() override;
> bool addRegBankSelect() override;
> bool addGlobalInstructionSelect() override;
> -#endif
> void addFastRegAlloc(FunctionPass *RegAllocPass) override;
> void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
> void addPreRegAlloc() override;
> @@ -756,7 +754,6 @@ bool GCNPassConfig::addInstSelector() {
> return false;
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool GCNPassConfig::addIRTranslator() {
> addPass(new IRTranslator());
> return false;
> @@ -777,8 +774,6 @@ bool GCNPassConfig::addGlobalInstruction
> return false;
> }
>
> -#endif
> -
> void GCNPassConfig::addPreRegAlloc() {
> if (LateCFGStructurize) {
> addPass(createAMDGPUMachineCFGStructurizerPass());
>
> Modified: llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt Thu Aug 3 14:52:25 2017
> @@ -12,28 +12,9 @@ tablegen(LLVM AMDGPUGenAsmWriter.inc -ge
> tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
> tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
> tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
> -endif()
> +tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
> add_public_tablegen_target(AMDGPUCommonTableGen)
>
> -# List of all GlobalISel files.
> -set(GLOBAL_ISEL_FILES
> - AMDGPUCallLowering.cpp
> - AMDGPUInstructionSelector.cpp
> - AMDGPULegalizerInfo.cpp
> - AMDGPURegisterBankInfo.cpp
> - )
> -
> -# Add GlobalISel files to the dependencies if the user wants to build it.
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
> -else()
> - set(GLOBAL_ISEL_BUILD_FILES"")
> - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
> -endif()
> -
> -
> add_llvm_target(AMDGPUCodeGen
> AMDILCFGStructurizer.cpp
> AMDGPUAliasAnalysis.cpp
> @@ -41,9 +22,12 @@ add_llvm_target(AMDGPUCodeGen
> AMDGPUAnnotateKernelFeatures.cpp
> AMDGPUAnnotateUniformValues.cpp
> AMDGPUAsmPrinter.cpp
> + AMDGPUCallLowering.cpp
> AMDGPUCodeGenPrepare.cpp
> AMDGPUFrameLowering.cpp
> + AMDGPULegalizerInfo.cpp
> AMDGPUTargetObjectFile.cpp
> + AMDGPUInstructionSelector.cpp
> AMDGPUIntrinsicInfo.cpp
> AMDGPUISelDAGToDAG.cpp
> AMDGPULowerIntrinsics.cpp
> @@ -61,6 +45,7 @@ add_llvm_target(AMDGPUCodeGen
> AMDGPUInstrInfo.cpp
> AMDGPUPromoteAlloca.cpp
> AMDGPURegAsmNames.inc.cpp
> + AMDGPURegisterBankInfo.cpp
> AMDGPURegisterInfo.cpp
> AMDGPURewriteOutArguments.cpp
> AMDGPUUnifyDivergentExitNodes.cpp
> @@ -105,7 +90,6 @@ add_llvm_target(AMDGPUCodeGen
> GCNIterativeScheduler.cpp
> GCNMinRegStrategy.cpp
> GCNRegPressure.cpp
> - ${GLOBAL_ISEL_BUILD_FILES}
> )
>
> add_subdirectory(AsmParser)
>
> Modified: llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCallLowering.cpp Thu Aug 3 14:52:25 2017
> @@ -26,10 +26,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "This shouldn't be built without GISel"
> -#endif
> -
> ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
> : CallLowering(&TLI) {}
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Thu Aug 3 14:52:25
> 2017
> @@ -25,10 +25,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> namespace {
>
> #define GET_GLOBALISEL_PREDICATE_BITSET
>
> Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Thu Aug 3 14:52:25 2017
> @@ -24,10 +24,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> static bool AEABI(const ARMSubtarget &ST) {
> return ST.isTargetAEABI() || ST.isTargetGNUAEABI() ||
> ST.isTargetMuslAEABI();
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu Aug 3 14:52:25
> 2017
> @@ -24,10 +24,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> // FIXME: TableGen this.
> // If it grows too much and TableGen still isn't ready to do the job,
> extract it
> // into an ARMGenRegisterBankInfo.def (similar to AArch64).
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Aug 3 14:52:25 2017
> @@ -13,11 +13,9 @@
>
> #include "ARM.h"
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> #include "ARMCallLowering.h"
> #include "ARMLegalizerInfo.h"
> #include "ARMRegisterBankInfo.h"
> -#endif
> #include "ARMSubtarget.h"
> #include "ARMFrameLowering.h"
> #include "ARMInstrInfo.h"
> @@ -30,13 +28,11 @@
> #include "llvm/ADT/StringRef.h"
> #include "llvm/ADT/Triple.h"
> #include "llvm/ADT/Twine.h"
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
> #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
> #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
> #include "llvm/CodeGen/GlobalISel/Legalizer.h"
> #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
> -#endif
> #include "llvm/CodeGen/MachineFunction.h"
> #include "llvm/IR/Function.h"
> #include "llvm/IR/GlobalValue.h"
> @@ -101,7 +97,6 @@ ARMFrameLowering *ARMSubtarget::initiali
> return new ARMFrameLowering(STI);
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> namespace {
>
> struct ARMGISelActualAccessor : public GISelAccessor {
> @@ -128,7 +123,6 @@ struct ARMGISelActualAccessor : public G
> };
>
> } // end anonymous namespace
> -#endif
>
> ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
> const std::string &FS,
> @@ -147,9 +141,6 @@ ARMSubtarget::ARMSubtarget(const Triple
> assert((isThumb() || hasARMOps()) &&
> "Target must either be thumb or support ARM operations!");
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> - GISelAccessor *GISel = new GISelAccessor();
> -#else
> ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
> GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
> GISel->Legalizer.reset(new ARMLegalizerInfo(*this));
> @@ -163,7 +154,6 @@ ARMSubtarget::ARMSubtarget(const Triple
> *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
>
> GISel->RegBankInfo.reset(RBI);
> -#endif
> setGISelAccessor(*GISel);
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Aug 3 14:52:25 2017
> @@ -333,12 +333,10 @@ public:
> void addIRPasses() override;
> bool addPreISel() override;
> bool addInstSelector() override;
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool addIRTranslator() override;
> bool addLegalizeMachineIR() override;
> bool addRegBankSelect() override;
> bool addGlobalInstructionSelect() override;
> -#endif
> void addPreRegAlloc() override;
> void addPreSched2() override;
> void addPreEmitPass() override;
> @@ -413,7 +411,6 @@ bool ARMPassConfig::addInstSelector() {
> return false;
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool ARMPassConfig::addIRTranslator() {
> addPass(new IRTranslator());
> return false;
> @@ -433,7 +430,6 @@ bool ARMPassConfig::addGlobalInstruction
> addPass(new InstructionSelect());
> return false;
> }
> -#endif
>
> void ARMPassConfig::addPreRegAlloc() {
> if (getOptLevel() != CodeGenOpt::None) {
>
> Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Aug 3 14:52:25 2017
> @@ -1,9 +1,7 @@
> set(LLVM_TARGET_DEFINITIONS ARM.td)
>
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
> - tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
> -endif()
> +tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
> +tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
> tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
> tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
> tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
> @@ -18,41 +16,30 @@ tablegen(LLVM ARMGenDisassemblerTables.i
> tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables)
> add_public_tablegen_target(ARMCommonTableGen)
>
> -# Add GlobalISel files if the user wants to build it.
> -set(GLOBAL_ISEL_FILES
> - ARMCallLowering.cpp
> - ARMInstructionSelector.cpp
> - ARMLegalizerInfo.cpp
> - ARMRegisterBankInfo.cpp
> - )
> -
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
> -else()
> - set(GLOBAL_ISEL_BUILD_FILES "")
> - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
> -endif()
> -
> add_llvm_target(ARMCodeGen
> A15SDOptimizer.cpp
> ARMAsmPrinter.cpp
> ARMBaseInstrInfo.cpp
> ARMBaseRegisterInfo.cpp
> + ARMCallLowering.cpp
> ARMConstantIslandPass.cpp
> ARMConstantPoolValue.cpp
> ARMExpandPseudoInsts.cpp
> ARMFastISel.cpp
> ARMFrameLowering.cpp
> ARMHazardRecognizer.cpp
> + ARMInstructionSelector.cpp
> ARMISelDAGToDAG.cpp
> ARMISelLowering.cpp
> ARMInstrInfo.cpp
> + ARMLegalizerInfo.cpp
> ARMLoadStoreOptimizer.cpp
> ARMMCInstLower.cpp
> ARMMachineFunctionInfo.cpp
> ARMMacroFusion.cpp
> ARMRegisterInfo.cpp
> ARMOptimizeBarriersPass.cpp
> + ARMRegisterBankInfo.cpp
> ARMSelectionDAGInfo.cpp
> ARMSubtarget.cpp
> ARMTargetMachine.cpp
> @@ -66,7 +53,6 @@ add_llvm_target(ARMCodeGen
> Thumb2InstrInfo.cpp
> Thumb2SizeReduction.cpp
> ARMComputeBlockSize.cpp
> - ${GLOBAL_ISEL_BUILD_FILES}
> )
>
> add_subdirectory(TargetInfo)
>
> Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Thu Aug 3 14:52:25 2017
> @@ -11,32 +11,15 @@ tablegen(LLVM X86GenFastISel.inc -gen-fa
> tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
> tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
> tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
> - tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
> -endif()
> +tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
> +tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
>
> add_public_tablegen_target(X86CommonTableGen)
>
> -# Add GlobalISel files if the build option was enabled.
> -set(GLOBAL_ISEL_FILES
> - X86CallLowering.cpp
> - X86LegalizerInfo.cpp
> - X86RegisterBankInfo.cpp
> - X86InstructionSelector.cpp
> - )
> -
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
> -else()
> - set(GLOBAL_ISEL_BUILD_FILES "")
> - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
> -endif()
> -
> -
> set(sources
> X86AsmPrinter.cpp
> X86CallFrameOptimization.cpp
> + X86CallLowering.cpp
> X86CmovConversion.cpp
> X86ExpandPseudo.cpp
> X86FastISel.cpp
> @@ -45,17 +28,20 @@ set(sources
> X86FixupSetCC.cpp
> X86FloatingPoint.cpp
> X86FrameLowering.cpp
> + X86InstructionSelector.cpp
> X86ISelDAGToDAG.cpp
> X86ISelLowering.cpp
> X86InterleavedAccess.cpp
> X86InstrFMA3Info.cpp
> X86InstrInfo.cpp
> X86EvexToVex.cpp
> + X86LegalizerInfo.cpp
> X86MCInstLower.cpp
> X86MachineFunctionInfo.cpp
> X86MacroFusion.cpp
> X86OptimizeLEAs.cpp
> X86PadShortFunction.cpp
> + X86RegisterBankInfo.cpp
> X86RegisterInfo.cpp
> X86SelectionDAGInfo.cpp
> X86ShuffleDecodeConstantPool.cpp
> @@ -67,7 +53,6 @@ set(sources
> X86WinAllocaExpander.cpp
> X86WinEHState.cpp
> X86CallingConv.cpp
> - ${GLOBAL_ISEL_BUILD_FILES}
> )
>
> add_llvm_target(X86CodeGen ${sources})
>
> Modified: llvm/trunk/lib/Target/X86/X86CallLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallLowering.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CallLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CallLowering.cpp Thu Aug 3 14:52:25 2017
> @@ -29,10 +29,6 @@ using namespace llvm;
>
> #include "X86GenCallingConv.inc"
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "This shouldn't be built without GISel"
> -#endif
> -
> X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
> : CallLowering(&TLI) {}
>
>
> Modified: llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def (original)
> +++ llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def Thu Aug 3 14:52:25
> 2017
> @@ -11,10 +11,6 @@
> /// \todo This should be generated by TableGen.
> //===----------------------------------------------------------------------===//
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> #ifdef GET_TARGET_REGBANK_INFO_IMPL
> RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
> /* StartIdx, Length, RegBank */
>
> Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Thu Aug 3 14:52:25
> 2017
> @@ -36,10 +36,6 @@
>
> using namespace llvm;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> namespace {
>
> #define GET_GLOBALISEL_PREDICATE_BITSET
>
> Modified: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp Thu Aug 3 14:52:25 2017
> @@ -22,10 +22,6 @@
> using namespace llvm;
> using namespace TargetOpcode;
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
> const X86TargetMachine &TM)
> : Subtarget(STI), TM(TM) {
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp Thu Aug 3 14:52:25
> 2017
> @@ -26,10 +26,6 @@ using namespace llvm;
> #define GET_TARGET_REGBANK_INFO_IMPL
> #include "X86GenRegisterBankInfo.def"
>
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> -#error "You shouldn't build this"
> -#endif
> -
> X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)
> : X86GenRegisterBankInfo() {
>
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Aug 3 14:52:25 2017
> @@ -13,21 +13,17 @@
>
> #include "X86.h"
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> #include "X86CallLowering.h"
> #include "X86LegalizerInfo.h"
> #include "X86RegisterBankInfo.h"
> -#endif
> #include "X86Subtarget.h"
> #include "MCTargetDesc/X86BaseInfo.h"
> #include "X86TargetMachine.h"
> #include "llvm/ADT/Triple.h"
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> #include "llvm/CodeGen/GlobalISel/CallLowering.h"
> #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
> #include "llvm/CodeGen/GlobalISel/Legalizer.h"
> #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
> -#endif
> #include "llvm/IR/Attributes.h"
> #include "llvm/IR/ConstantRange.h"
> #include "llvm/IR/Function.h"
> @@ -352,7 +348,6 @@ X86Subtarget &X86Subtarget::initializeSu
> return *this;
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> namespace {
>
> struct X86GISelActualAccessor : public GISelAccessor {
> @@ -379,7 +374,6 @@ struct X86GISelActualAccessor : public G
> };
>
> } // end anonymous namespace
> -#endif
>
> X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
> const X86TargetMachine &TM,
> @@ -405,9 +399,6 @@ X86Subtarget::X86Subtarget(const Triple
> setPICStyle(PICStyles::StubPIC);
> else if (isTargetELF())
> setPICStyle(PICStyles::GOT);
> -#ifndef LLVM_BUILD_GLOBAL_ISEL
> - GISelAccessor *GISel = new GISelAccessor();
> -#else
> X86GISelActualAccessor *GISel = new X86GISelActualAccessor();
>
> GISel->CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
> @@ -416,7 +407,6 @@ X86Subtarget::X86Subtarget(const Triple
> auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
> GISel->RegBankInfo.reset(RBI);
> GISel->InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
> -#endif
> setGISelAccessor(*GISel);
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Aug 3 14:52:25 2017
> @@ -306,12 +306,10 @@ public:
>
> void addIRPasses() override;
> bool addInstSelector() override;
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool addIRTranslator() override;
> bool addLegalizeMachineIR() override;
> bool addRegBankSelect() override;
> bool addGlobalInstructionSelect() override;
> -#endif
> bool addILPOpts() override;
> bool addPreISel() override;
> void addPreRegAlloc() override;
> @@ -361,7 +359,6 @@ bool X86PassConfig::addInstSelector() {
> return false;
> }
>
> -#ifdef LLVM_BUILD_GLOBAL_ISEL
> bool X86PassConfig::addIRTranslator() {
> addPass(new IRTranslator());
> return false;
> @@ -381,7 +378,6 @@ bool X86PassConfig::addGlobalInstruction
> addPass(new InstructionSelect());
> return false;
> }
> -#endif
>
> bool X86PassConfig::addILPOpts() {
> addPass(&EarlyIfConverterID);
>
> Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-config/CMakeLists.txt (original)
> +++ llvm/trunk/tools/llvm-config/CMakeLists.txt Thu Aug 3 14:52:25 2017
> @@ -37,11 +37,7 @@ set(LLVM_CXXFLAGS "${CMAKE_CXX_FLAGS} ${
> set(LLVM_BUILD_SYSTEM cmake)
> set(LLVM_HAS_RTTI ${LLVM_CONFIG_HAS_RTTI})
> set(LLVM_DYLIB_VERSION
> "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}${LLVM_VERSION_SUFFIX}")
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - set(LLVM_HAS_GLOBAL_ISEL "ON")
> -else()
> - set(LLVM_HAS_GLOBAL_ISEL "OFF")
> -endif()
> +set(LLVM_HAS_GLOBAL_ISEL "ON")
>
> # Use the C++ link flags, since they should be a superset of C link flags.
> set(LLVM_LDFLAGS "${CMAKE_CXX_LINK_FLAGS}")
>
> Modified: llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt?rev=309990&r1=309989&r2=309990&view=diff
> ==============================================================================
> --- llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt (original)
> +++ llvm/trunk/unittests/CodeGen/GlobalISel/CMakeLists.txt Thu Aug 3
> 14:52:25 2017
> @@ -3,8 +3,6 @@ set(LLVM_LINK_COMPONENTS
> CodeGen
> )
>
> -if(LLVM_BUILD_GLOBAL_ISEL)
> - add_llvm_unittest(GlobalISelTests
> - LegalizerInfoTest.cpp
> - )
> -endif()
> +add_llvm_unittest(GlobalISelTests
> + LegalizerInfoTest.cpp
> + )
>
>
> _______________________________________________
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>
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