[llvm] r310172 - IPRA: Don't crash on null getCallPreservedMask

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Sat Aug  5 00:50:18 2017
New Revision: 310172

URL: http://llvm.org/viewvc/llvm-project?rev=310172&view=rev
Log:
IPRA: Don't crash on null getCallPreservedMask

Kernels aren't callable, so they don't have a call preserved mask.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/ipra.ll
Modified:
    llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp

Modified: llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp?rev=310172&r1=310171&r2=310172&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp Sat Aug  5 00:50:18 2017
@@ -128,9 +128,11 @@ bool RegUsageInfoCollector::runOnMachine
   if (!TargetFrameLowering::isSafeForNoCSROpt(F)) {
     const uint32_t *CallPreservedMask =
         TRI->getCallPreservedMask(MF, F->getCallingConv());
-    // Set callee saved register as preserved.
-    for (unsigned i = 0; i < RegMaskSize; ++i)
-      RegMask[i] = RegMask[i] | CallPreservedMask[i];
+    if (CallPreservedMask) {
+      // Set callee saved register as preserved.
+      for (unsigned i = 0; i < RegMaskSize; ++i)
+        RegMask[i] = RegMask[i] | CallPreservedMask[i];
+    }
   } else {
     ++NumCSROpt;
     DEBUG(dbgs() << MF.getName()

Added: llvm/trunk/test/CodeGen/AMDGPU/ipra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ipra.ll?rev=310172&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ipra.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/ipra.ll Sat Aug  5 00:50:18 2017
@@ -0,0 +1,12 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -enable-ipra < %s | FileCheck -check-prefix=GCN %s
+
+; Kernels are not called, so there is no call preserved mask.
+; GCN-LABEL: {{^}}kernel:
+; GCN: flat_store_dword
+define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) #0 {
+entry:
+  store i32 0, i32 addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind }