[llvm] r309898 - AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Wed Aug  2 15:56:30 2017
New Revision: 309898

URL: http://llvm.org/viewvc/llvm-project?rev=309898&view=rev
Log:
AMDGPU/GlobalISel: Mark 32-bit G_FMUL as legal

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D36218

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=309898&r1=309897&r2=309898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Wed Aug  2 15:56:30 2017
@@ -53,6 +53,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
 
   setAction({G_FCONSTANT, S32}, Legal);
 
+  setAction({G_FMUL, S32}, Legal);
+
   setAction({G_GEP, P1}, Legal);
   setAction({G_GEP, P2}, Legal);
   setAction({G_GEP, 1, S64}, Legal);

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir?rev=309898&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir Wed Aug  2 15:56:30 2017
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_fmul() { ret void }
+...
+
+---
+name:            test_fmul
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body: |
+  bb.0:
+    liveins: %vgpr0, %vgpr1
+    ; CHECK-LABEL: name: test_fmul
+    ; CHECK: %2(s32) = G_FMUL %0, %1
+
+    %0(s32) = COPY %vgpr0
+    %1(s32) = COPY %vgpr1
+    %2(s32) = G_FMUL %0, %1
+...