[PATCH] D36248: [AArch64] Fix an assertion for pre-index generation with unscaled loads/stores.

[Chad Rosier via Phabricator via llvm-commits]

mcrosier created this revision.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

This looks to be as simple as we were missing the necessary opcodes from the switch statement.  In trying to write IR test cases I found that ISel kept generating the pre-inc forms during lower, so I ended up writing all the tests in MIR.  I suspect this is also the reason why this bug existed for so long without being discovered.

I didn't add the cases to the pre-index forms because the main loops skip this optimization for unscaled loads/stores.  I'm not sure why this is the case, but perhaps that justs a missed opportunities to be addressed by a later patch (and if so the missing pre-index cases can be added then).

This should fix PR34035.

Chad


https://reviews.llvm.org/D36248

Files:
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir

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