[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Haicheng Wu via Phabricator via llvm-commits]

haicheng added inline comments.


================
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2767
   case ISD::Constant: {
-    // Materialize zero constants as copies from WZR/XZR.  This allows
-    // the coalescer to propagate these into other instructions.
+    // If all uses of zero constants are copies to virutal regs, replace the
+    // conatants with WZR/XZR.  Otherwise, materialize zero constants as copies
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gberry wrote:
> Would it not make sense to replace any use of constant 0 with wzr/xzr when it is legal?
I agree with you.  I started with replacing any constant 0 with wzr/xzr, but triggered a lot of assertions.  For example, wzr/xzr is not expected to appear as the condition of a conditional branch.  Then, I  narrowed down to CopyToReg only, but still triggered some assertions when copying wzr/xzr to another physical register.  Now, I narrow down to the most common situation, copying constant zero to a virtual reg, no assertion is trigged and performance looks good.


Repository:
  rL LLVM

https://reviews.llvm.org/D36104