[PATCH] D36160: Liveness issues in tail merging, and the ARM::LR saved-but-not-restored

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz created this revision.
Herald added subscribers: kbarton, kristof.beyls, javed.absar, nemanjai, sdardis, aemerson.

This is a follow-up to this thread:
http://lists.llvm.org/pipermail/llvm-dev/2017-July/115909.html

This patch has a few things packed together and is not really intended to be in the final form, but to demonstrate the approach for now.

The original issue was with the tail merging leaving inconsistent liveness information around.  That is addressed in this patch by adding IMPLICIT_DEFs where needed.  LivePhysRegs is used to determine whether something is a live-in to a block, and here's where the remaining 90% of this patch comes from:
On ARM, if MBB is a return block, LivePhysRegs will add LR to its live-ins, if LR is in CalleeSavedInfo.  It does that for each register in CSI because the assumption is that if something is saved and restored, then it is live outside of the function.  The problem with LR is that it is not restored (in many cases) and so it doesn't need to be treated as a live-out from the function, and subsequently as a live-in to the return block.  In tail merging, having it as a live-in to a block caused IMPLICIT_DEFs defining LR to appear in some predecessors, which then prevented certain macro-fusion-like optimizations (merging cmp with a branch) from happening later on.

The approach to deal with it taken here is to add a field in CalleeSavedInfo indicating that the saved register is actually restored.  It is set to "true" by default, and target's implementation of restoreCalleeSavedRegisters should only reset it to "false" when the register is not restored.  Currently, this only applies to LR on ARM. This has the consequence  that the CSI parameter is no longer "const", which is not something I'm a fan of.  LivePhysRegs is the user of that information when it adds block live-outs.


Repository:
  rL LLVM

https://reviews.llvm.org/D36160

Files:
  include/llvm/CodeGen/MachineFrameInfo.h
  include/llvm/Target/TargetFrameLowering.h
  lib/CodeGen/BranchFolding.cpp
  lib/CodeGen/BranchFolding.h
  lib/CodeGen/LivePhysRegs.cpp
  lib/CodeGen/PrologEpilogInserter.cpp
  lib/Target/AArch64/AArch64FrameLowering.cpp
  lib/Target/AArch64/AArch64FrameLowering.h
  lib/Target/ARM/ARMFrameLowering.cpp
  lib/Target/ARM/ARMFrameLowering.h
  lib/Target/ARM/Thumb1FrameLowering.cpp
  lib/Target/ARM/Thumb1FrameLowering.h
  lib/Target/AVR/AVRFrameLowering.cpp
  lib/Target/AVR/AVRFrameLowering.h
  lib/Target/Hexagon/HexagonFrameLowering.h
  lib/Target/MSP430/MSP430FrameLowering.cpp
  lib/Target/MSP430/MSP430FrameLowering.h
  lib/Target/Mips/Mips16FrameLowering.cpp
  lib/Target/Mips/Mips16FrameLowering.h
  lib/Target/PowerPC/PPCFrameLowering.cpp
  lib/Target/PowerPC/PPCFrameLowering.h
  lib/Target/SystemZ/SystemZFrameLowering.cpp
  lib/Target/SystemZ/SystemZFrameLowering.h
  lib/Target/X86/X86FrameLowering.cpp
  lib/Target/X86/X86FrameLowering.h
  lib/Target/XCore/XCoreFrameLowering.cpp
  lib/Target/XCore/XCoreFrameLowering.h
  test/CodeGen/Hexagon/branchfolder-insert-impdef.mir
  test/CodeGen/Hexagon/livephysregs-lane-masks2.mir

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