[PATCH] D36123: [InstCombine] Remove explicit check for impossible condition. Replace with assert

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL309690: [InstCombine] Remove explicit check for impossible condition. Replace with… (authored by ctopper).

Changed prior to commit:
  https://reviews.llvm.org/D36123?vs=109032&id=109125#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36123

Files:
  llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp


Index: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
===================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -534,7 +534,8 @@
 
       // If the input sign bit is known to be zero, or if none of the top bits
       // are demanded, turn this into an unsigned shift right.
-      if (BitWidth <= ShiftAmt || Known.Zero[BitWidth-ShiftAmt-1] ||
+      assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
+      if (Known.Zero[BitWidth-ShiftAmt-1] ||
           !DemandedMask.intersects(HighBits)) {
         BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
                                                           I->getOperand(1));


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