[PATCH] D36152: [ARM] Add registers to debuginfo MIR test cases.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

MIRParserImpl::computeFunctionProperties uses MRI.getNumVirtRegs() to
set the NoVReg property. By adding a bunch of registers to the MIR test
cases, the NoVReg property is not set when importing the MIR. Otherwise
NoVReg is set after instruction selection while the machine instructions
still contain virtual registers, causing expensive checks to fail.


https://reviews.llvm.org/D36152

Files:
  test/DebugInfo/MIR/ARM/split-superreg-complex.mir
  test/DebugInfo/MIR/ARM/split-superreg-piece.mir
  test/DebugInfo/MIR/ARM/split-superreg.mir


Index: test/DebugInfo/MIR/ARM/split-superreg.mir
===================================================================
--- test/DebugInfo/MIR/ARM/split-superreg.mir
+++ test/DebugInfo/MIR/ARM/split-superreg.mir
@@ -76,6 +76,22 @@
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprnopc }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gprnopc }
+  - { id: 4, class: gprnopc }
+  - { id: 5, class: gprnopc }
+  - { id: 6, class: gprnopc }
+  - { id: 7, class: gprnopc }
+  - { id: 8, class: gprnopc }
+  - { id: 9, class: gpr }
+  - { id: 10, class: gprnopc }
+  - { id: 11, class: gprnopc }
+  - { id: 12, class: gprnopc }
+  - { id: 13, class: gpr }
+  - { id: 14, class: gprnopc }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', 
                         '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', 
                         '%r5', '%r6', '%r7', '%r8', '%r10', '%r11', '%s16', 
Index: test/DebugInfo/MIR/ARM/split-superreg-piece.mir
===================================================================
--- test/DebugInfo/MIR/ARM/split-superreg-piece.mir
+++ test/DebugInfo/MIR/ARM/split-superreg-piece.mir
@@ -76,6 +76,22 @@
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprnopc }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gprnopc }
+  - { id: 4, class: gprnopc }
+  - { id: 5, class: gprnopc }
+  - { id: 6, class: gprnopc }
+  - { id: 7, class: gprnopc }
+  - { id: 8, class: gprnopc }
+  - { id: 9, class: gpr }
+  - { id: 10, class: gprnopc }
+  - { id: 11, class: gprnopc }
+  - { id: 12, class: gprnopc }
+  - { id: 13, class: gpr }
+  - { id: 14, class: gprnopc }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', 
                         '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', 
                         '%r5', '%r6', '%r7', '%r8', '%r10', '%r11', '%s16', 
Index: test/DebugInfo/MIR/ARM/split-superreg-complex.mir
===================================================================
--- test/DebugInfo/MIR/ARM/split-superreg-complex.mir
+++ test/DebugInfo/MIR/ARM/split-superreg-complex.mir
@@ -73,6 +73,22 @@
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
+registers:
+  - { id: 0, class: gprnopc }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gprnopc }
+  - { id: 4, class: gprnopc }
+  - { id: 5, class: gprnopc }
+  - { id: 6, class: gprnopc }
+  - { id: 7, class: gprnopc }
+  - { id: 8, class: gprnopc }
+  - { id: 9, class: gpr }
+  - { id: 10, class: gprnopc }
+  - { id: 11, class: gprnopc }
+  - { id: 12, class: gprnopc }
+  - { id: 13, class: gpr }
+  - { id: 14, class: gprnopc }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', 
                         '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', 
                         '%r5', '%r6', '%r7', '%r8', '%r10', '%r11', '%s16', 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D36152.109123.patch
Type: text/x-patch
Size: 3045 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170801/2133a4aa/attachment.bin>