[PATCH] D34815: [Power9] Spill gprs to vector registers rather than stack

[Zaara Syeda via Phabricator via llvm-commits]

syzaara added inline comments.


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Comment at: test/CodeGen/PowerPC/gpr-vsr-spill2.ll:1
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-enable-gpr-to-vsr-spills  < %s | FileCheck %s
+
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hfinkel wrote:
> Having this as an IR-level test seems fragile. Could you make this into a (simpler) MIR test that shows the behavior?
I tried to create an MIR case using this, but the limitation with MIR tests identified in https://reviews.llvm.org/D33562 with MachineFunctionInfo not being saved/dumped as part of emitting .mir leads to machine verified errors. I tried to change the global vars to local vars to get around this limitation. However, doing that no longer reproduces the narrowed case so I will leave this as an IR test.


https://reviews.llvm.org/D34815