[llvm] r309323 - [AArch64] Fix legality info passed to demanded bits for TBI opt.

[Hans Wennborg via llvm-commits]

Merged to 5.0 in r309586.

On Thu, Jul 27, 2017 at 2:27 PM, Ahmed Bougacha via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ab
> Date: Thu Jul 27 14:27:25 2017
> New Revision: 309323
>
> URL: http://llvm.org/viewvc/llvm-project?rev=309323&view=rev
> Log:
> [AArch64] Fix legality info passed to demanded bits for TBI opt.
>
> The (seldom-used) TBI-aware optimization had a typo lying dormant since
> it was first introduced, in r252573:  when asking for demanded bits, it
> told TLI that it was running after legalize, where the opposite was
> true.
>
> This is an important piece of information, that the demanded bits
> analysis uses to make assumptions about the node.  r301019 added such an
> assumption, which was broken by the TBI combine.
>
> Instead, pass the correct flags to TLO.
>
> Modified:
>     llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>     llvm/trunk/test/CodeGen/AArch64/tbi.ll
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=309323&r1=309322&r2=309323&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Jul 27 14:27:25 2017
> @@ -9585,8 +9585,8 @@ static bool performTBISimplification(SDV
>                                       SelectionDAG &DAG) {
>    APInt DemandedMask = APInt::getLowBitsSet(64, 56);
>    KnownBits Known;
> -  TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
> -                                        DCI.isBeforeLegalizeOps());
> +  TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
> +                                        !DCI.isBeforeLegalizeOps());
>    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
>    if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) {
>      DCI.CommitTargetLoweringOpt(TLO);
>
> Modified: llvm/trunk/test/CodeGen/AArch64/tbi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tbi.ll?rev=309323&r1=309322&r2=309323&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/tbi.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/tbi.ll Thu Jul 27 14:27:25 2017
> @@ -100,3 +100,14 @@ define i32 @ld_and32_narrower(i64 %p) {
>    %load = load i32, i32* %cast
>    ret i32 %load
>  }
> +
> +; BOTH-LABEL:ld_and8:
> +; BOTH: and x
> +define i32 @ld_and8(i64 %base, i8 %off) {
> +  %off_masked = and i8 %off, 63
> +  %off_64 = zext i8 %off_masked to i64
> +  %p = add i64 %base, %off_64
> +  %cast = inttoptr i64 %p to i32*
> +  %load = load i32, i32* %cast
> +  ret i32 %load
> +}
>
>
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