[llvm] r309541 - [PowerPC] Change method names; NFC
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 30 23:27:09 PDT 2017
Author: inouehrs
Date: Sun Jul 30 23:27:09 2017
New Revision: 309541
URL: http://llvm.org/viewvc/llvm-project?rev=309541&view=rev
Log:
[PowerPC] Change method names; NFC
Changed method names based on the discussion in https://reviews.llvm.org/D34986:
getInt64 -> selectI64Imm,
getInt64Count -> selectI64ImmInstrCount.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=309541&r1=309540&r2=309541&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sun Jul 30 23:27:09 2017
@@ -643,8 +643,8 @@ bool PPCDAGToDAGISel::tryBitfieldInsert(
}
// Predict the number of instructions that would be generated by calling
-// getInt64(N).
-static unsigned getInt64CountDirect(int64_t Imm) {
+// selectI64Imm(N).
+static unsigned selectI64ImmInstrCountDirect(int64_t Imm) {
// Assume no remaining bits.
unsigned Remainder = 0;
// Assume no shift required.
@@ -712,8 +712,8 @@ static uint64_t Rot64(uint64_t Imm, unsi
return (Imm << R) | (Imm >> (64 - R));
}
-static unsigned getInt64Count(int64_t Imm) {
- unsigned Count = getInt64CountDirect(Imm);
+static unsigned selectI64ImmInstrCount(int64_t Imm) {
+ unsigned Count = selectI64ImmInstrCountDirect(Imm);
// If the instruction count is 1 or 2, we do not need further analysis
// since rotate + load constant requires at least 2 instructions.
@@ -722,10 +722,10 @@ static unsigned getInt64Count(int64_t Im
for (unsigned r = 1; r < 63; ++r) {
uint64_t RImm = Rot64(Imm, r);
- unsigned RCount = getInt64CountDirect(RImm) + 1;
+ unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
Count = std::min(Count, RCount);
- // See comments in getInt64 for an explanation of the logic below.
+ // See comments in selectI64Imm for an explanation of the logic below.
unsigned LS = findLastSet(RImm);
if (LS != r-1)
continue;
@@ -733,17 +733,17 @@ static unsigned getInt64Count(int64_t Im
uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
uint64_t RImmWithOnes = RImm | OnesMask;
- RCount = getInt64CountDirect(RImmWithOnes) + 1;
+ RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
Count = std::min(Count, RCount);
}
return Count;
}
-// Select a 64-bit constant. For cost-modeling purposes, getInt64Count
+// Select a 64-bit constant. For cost-modeling purposes, selectI64ImmInstrCount
// (above) needs to be kept in sync with this function.
-static SDNode *getInt64Direct(SelectionDAG *CurDAG, const SDLoc &dl,
- int64_t Imm) {
+static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
+ int64_t Imm) {
// Assume no remaining bits.
unsigned Remainder = 0;
// Assume no shift required.
@@ -825,13 +825,14 @@ static SDNode *getInt64Direct(SelectionD
return Result;
}
-static SDNode *getInt64(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) {
- unsigned Count = getInt64CountDirect(Imm);
+static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl,
+ int64_t Imm) {
+ unsigned Count = selectI64ImmInstrCountDirect(Imm);
// If the instruction count is 1 or 2, we do not need further analysis
// since rotate + load constant requires at least 2 instructions.
if (Count <= 2)
- return getInt64Direct(CurDAG, dl, Imm);
+ return selectI64ImmDirect(CurDAG, dl, Imm);
unsigned RMin = 0;
@@ -840,7 +841,7 @@ static SDNode *getInt64(SelectionDAG *Cu
for (unsigned r = 1; r < 63; ++r) {
uint64_t RImm = Rot64(Imm, r);
- unsigned RCount = getInt64CountDirect(RImm) + 1;
+ unsigned RCount = selectI64ImmInstrCountDirect(RImm) + 1;
if (RCount < Count) {
Count = RCount;
RMin = r;
@@ -863,7 +864,7 @@ static SDNode *getInt64(SelectionDAG *Cu
uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
uint64_t RImmWithOnes = RImm | OnesMask;
- RCount = getInt64CountDirect(RImmWithOnes) + 1;
+ RCount = selectI64ImmInstrCountDirect(RImmWithOnes) + 1;
if (RCount < Count) {
Count = RCount;
RMin = r;
@@ -873,24 +874,24 @@ static SDNode *getInt64(SelectionDAG *Cu
}
if (!RMin)
- return getInt64Direct(CurDAG, dl, Imm);
+ return selectI64ImmDirect(CurDAG, dl, Imm);
auto getI32Imm = [CurDAG, dl](unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
};
- SDValue Val = SDValue(getInt64Direct(CurDAG, dl, MatImm), 0);
+ SDValue Val = SDValue(selectI64ImmDirect(CurDAG, dl, MatImm), 0);
return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
getI32Imm(64 - RMin), getI32Imm(MaskEnd));
}
// Select a 64-bit constant.
-static SDNode *getInt64(SelectionDAG *CurDAG, SDNode *N) {
+static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
SDLoc dl(N);
// Get 64 bit value.
int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
- return getInt64(CurDAG, dl, Imm);
+ return selectI64Imm(CurDAG, dl, Imm);
}
namespace {
@@ -1730,7 +1731,7 @@ class BitPermutationSelector {
NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
(unsigned) (ANDIMask != 0 && ANDISMask != 0);
else
- NumAndInsts += getInt64Count(Mask) + /* and */ 1;
+ NumAndInsts += selectI64ImmInstrCount(Mask) + /* and */ 1;
unsigned NumRLInsts = 0;
bool FirstBG = true;
@@ -1799,7 +1800,7 @@ class BitPermutationSelector {
TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
ANDIVal, ANDISVal), 0);
} else {
- TotalVal = SDValue(getInt64(CurDAG, dl, Mask), 0);
+ TotalVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
TotalVal =
SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
VRot, TotalVal), 0);
@@ -1942,9 +1943,9 @@ class BitPermutationSelector {
Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
ANDIVal, ANDISVal), 0);
} else {
- if (InstCnt) *InstCnt += getInt64Count(Mask) + /* and */ 1;
+ if (InstCnt) *InstCnt += selectI64ImmInstrCount(Mask) + /* and */ 1;
- SDValue MaskVal = SDValue(getInt64(CurDAG, dl, Mask), 0);
+ SDValue MaskVal = SDValue(selectI64Imm(CurDAG, dl, Mask), 0);
Res =
SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
Res, MaskVal), 0);
@@ -3081,7 +3082,7 @@ void PPCDAGToDAGISel::Select(SDNode *N)
case ISD::Constant:
if (N->getValueType(0) == MVT::i64) {
- ReplaceNode(N, getInt64(CurDAG, N));
+ ReplaceNode(N, selectI64Imm(CurDAG, N));
return;
}
break;
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