[llvm] r309469 - [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
Eugene Zelenko via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 28 17:56:56 PDT 2017
Author: eugenezelenko
Date: Fri Jul 28 17:56:56 2017
New Revision: 309469
URL: http://llvm.org/viewvc/llvm-project?rev=309469&view=rev
Log:
[Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonGenInsert.cpp ---------------------------------------------===//
+//===- HexagonGenInsert.cpp -----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -14,6 +14,7 @@
#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
@@ -190,7 +191,7 @@ namespace {
UnsignedMap() = default;
private:
- typedef DenseMap<unsigned,unsigned> BaseType;
+ using BaseType = DenseMap<unsigned, unsigned>;
};
// A utility to establish an ordering between virtual registers:
@@ -273,7 +274,8 @@ namespace {
const BitTracker &BT;
private:
- typedef std::vector<const BitTracker::RegisterCell*> CellVectType;
+ using CellVectType = std::vector<const BitTracker::RegisterCell *>;
+
CellVectType CVect;
};
@@ -367,7 +369,7 @@ bool RegisterCellBitCompareSel::operator
namespace {
class OrderedRegisterList {
- typedef std::vector<unsigned> ListType;
+ using ListType = std::vector<unsigned>;
public:
OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {}
@@ -384,8 +386,9 @@ namespace {
return Seq.size();
}
- typedef ListType::iterator iterator;
- typedef ListType::const_iterator const_iterator;
+ using iterator = ListType::iterator;
+ using const_iterator = ListType::const_iterator;
+
iterator begin() { return Seq.begin(); }
iterator end() { return Seq.end(); }
const_iterator begin() const { return Seq.begin(); }
@@ -469,7 +472,7 @@ namespace {
return OS;
}
- typedef std::pair<IFRecord,RegisterSet> IFRecordWithRegSet;
+ using IFRecordWithRegSet = std::pair<IFRecord, RegisterSet>;
} // end anonymous namespace
@@ -486,7 +489,7 @@ namespace {
public:
static char ID;
- HexagonGenInsert() : MachineFunctionPass(ID), HII(nullptr), HRI(nullptr) {
+ HexagonGenInsert() : MachineFunctionPass(ID) {
initializeHexagonGenInsertPass(*PassRegistry::getPassRegistry());
}
@@ -503,7 +506,7 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF) override;
private:
- typedef DenseMap<std::pair<unsigned,unsigned>,unsigned> PairMapType;
+ using PairMapType = DenseMap<std::pair<unsigned, unsigned>, unsigned>;
void buildOrderingMF(RegisterOrdering &RO) const;
void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
@@ -539,13 +542,13 @@ namespace {
bool removeDeadCode(MachineDomTreeNode *N);
// IFRecord coupled with a set of potentially removable registers:
- typedef std::vector<IFRecordWithRegSet> IFListType;
- typedef DenseMap<unsigned,IFListType> IFMapType; // vreg -> IFListType
+ using IFListType = std::vector<IFRecordWithRegSet>;
+ using IFMapType = DenseMap<unsigned, IFListType>; // vreg -> IFListType
void dump_map() const;
- const HexagonInstrInfo *HII;
- const HexagonRegisterInfo *HRI;
+ const HexagonInstrInfo *HII = nullptr;
+ const HexagonRegisterInfo *HRI = nullptr;
MachineFunction *MFN;
MachineRegisterInfo *MRI;
@@ -557,12 +560,13 @@ namespace {
IFMapType IFMap;
};
- char HexagonGenInsert::ID = 0;
-
} // end anonymous namespace
+char HexagonGenInsert::ID = 0;
+
void HexagonGenInsert::dump_map() const {
- typedef IFMapType::const_iterator iterator;
+ using iterator = IFMapType::const_iterator;
+
for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
dbgs() << " " << PrintReg(I->first, HRI) << ":\n";
const IFListType &LL = I->second;
@@ -574,12 +578,16 @@ void HexagonGenInsert::dump_map() const
void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
unsigned Index = 0;
- typedef MachineFunction::const_iterator mf_iterator;
+
+ using mf_iterator = MachineFunction::const_iterator;
+
for (mf_iterator A = MFN->begin(), Z = MFN->end(); A != Z; ++A) {
const MachineBasicBlock &B = *A;
if (!CMS->BT.reached(&B))
continue;
- typedef MachineBasicBlock::const_iterator mb_iterator;
+
+ using mb_iterator = MachineBasicBlock::const_iterator;
+
for (mb_iterator I = B.begin(), E = B.end(); I != E; ++I) {
const MachineInstr *MI = &*I;
for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
@@ -604,7 +612,9 @@ void HexagonGenInsert::buildOrderingBT(R
// ordering RB), and then sort it using the RegisterCell comparator.
BitValueOrdering BVO(RB);
RegisterCellLexCompare LexCmp(BVO, *CMS);
- typedef std::vector<unsigned> SortableVectorType;
+
+ using SortableVectorType = std::vector<unsigned>;
+
SortableVectorType VRs;
for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I)
VRs.push_back(I->first);
@@ -736,7 +746,9 @@ unsigned HexagonGenInsert::distance(cons
unsigned ToRPO = RPO.lookup(ToN);
unsigned MaxD = 0;
- typedef MachineBasicBlock::const_pred_iterator pred_iterator;
+
+ using pred_iterator = MachineBasicBlock::const_pred_iterator;
+
for (pred_iterator I = ToB->pred_begin(), E = ToB->pred_end(); I != E; ++I) {
const MachineBasicBlock *PB = *I;
// Skip back edges. Also, if FromB is a predecessor of ToB, the distance
@@ -775,17 +787,18 @@ bool HexagonGenInsert::findRecordInsertF
if (AVs.size() == 0)
return false;
- typedef OrderedRegisterList::iterator iterator;
+ using iterator = OrderedRegisterList::iterator;
+
BitValueOrdering BVO(BaseOrd);
const BitTracker::RegisterCell &RC = CMS->lookup(VR);
uint16_t W = RC.width();
- typedef std::pair<unsigned,uint16_t> RSRecord; // (reg,shift)
- typedef std::vector<RSRecord> RSListType;
+ using RSRecord = std::pair<unsigned, uint16_t>; // (reg,shift)
+ using RSListType = std::vector<RSRecord>;
// Have a map, with key being the matching prefix length, and the value
// being the list of pairs (R,S), where R's prefix matches VR at S.
// (DenseMap<uint16_t,RSListType> fails to instantiate.)
- typedef DenseMap<unsigned,RSListType> LRSMapType;
+ using LRSMapType = DenseMap<unsigned, RSListType>;
LRSMapType LM;
// Conceptually, rotate the cell RC right (i.e. towards the LSB) by S,
@@ -1018,7 +1031,7 @@ void HexagonGenInsert::computeRemovableR
void HexagonGenInsert::pruneEmptyLists() {
// Remove all entries from the map, where the register has no insert forms
// associated with it.
- typedef SmallVector<IFMapType::iterator,16> IterListType;
+ using IterListType = SmallVector<IFMapType::iterator, 16>;
IterListType Prune;
for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
if (I->second.empty())
@@ -1159,7 +1172,9 @@ void HexagonGenInsert::pruneCandidates()
pruneCoveredSets(I->first);
UnsignedMap RPO;
- typedef ReversePostOrderTraversal<const MachineFunction*> RPOTType;
+
+ using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;
+
RPOTType RPOT(MFN);
unsigned RPON = 0;
for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
@@ -1191,7 +1206,7 @@ namespace {
: UseC(UC), BaseOrd(BO) {}
bool operator() (const IFRecordWithRegSet &A,
- const IFRecordWithRegSet &B) const;
+ const IFRecordWithRegSet &B) const;
private:
void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
@@ -1266,8 +1281,9 @@ void HexagonGenInsert::selectCandidates(
}
for (unsigned R = AllRMs.find_first(); R; R = AllRMs.find_next(R)) {
- typedef MachineRegisterInfo::use_nodbg_iterator use_iterator;
- typedef SmallSet<const MachineInstr*,16> InstrSet;
+ using use_iterator = MachineRegisterInfo::use_nodbg_iterator;
+ using InstrSet = SmallSet<const MachineInstr *, 16>;
+
InstrSet UIs;
// Count as the number of instructions in which R is used, not the
// number of operands.
@@ -1561,7 +1577,9 @@ bool HexagonGenInsert::runOnMachineFunct
// Filter out vregs beyond the cutoff.
if (VRegIndexCutoff.getPosition()) {
unsigned Cutoff = VRegIndexCutoff;
- typedef SmallVector<IFMapType::iterator,16> IterListType;
+
+ using IterListType = SmallVector<IFMapType::iterator, 16>;
+
IterListType Out;
for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
unsigned Idx = TargetRegisterInfo::virtReg2Index(I->first);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonGenMux.cpp ------------------------------------------------===//
+//===- HexagonGenMux.cpp --------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -26,6 +26,7 @@
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/LivePhysRegs.h"
@@ -41,6 +42,7 @@
#include "llvm/Pass.h"
#include "llvm/Support/MathExtras.h"
#include <algorithm>
+#include <cassert>
#include <iterator>
#include <limits>
#include <utility>
@@ -109,9 +111,9 @@ namespace {
Def2(&D2) {}
};
- typedef DenseMap<MachineInstr*,unsigned> InstrIndexMap;
- typedef DenseMap<unsigned,DefUseInfo> DefUseInfoMap;
- typedef SmallVector<MuxInfo,4> MuxInfoList;
+ using InstrIndexMap = DenseMap<MachineInstr *, unsigned>;
+ using DefUseInfoMap = DenseMap<unsigned, DefUseInfo>;
+ using MuxInfoList = SmallVector<MuxInfo, 4>;
bool isRegPair(unsigned Reg) const {
return Hexagon::DoubleRegsRegClass.contains(Reg);
@@ -129,10 +131,10 @@ namespace {
bool genMuxInBlock(MachineBasicBlock &B);
};
- char HexagonGenMux::ID = 0;
-
} // end anonymous namespace
+char HexagonGenMux::ID = 0;
+
INITIALIZE_PASS(HexagonGenMux, "hexagon-gen-mux",
"Hexagon generate mux instructions", false, false)
@@ -220,7 +222,8 @@ bool HexagonGenMux::genMuxInBlock(Machin
DefUseInfoMap DUM;
buildMaps(B, I2X, DUM);
- typedef DenseMap<unsigned,CondsetInfo> CondsetMap;
+ using CondsetMap = DenseMap<unsigned, CondsetInfo>;
+
CondsetMap CM;
MuxInfoList ML;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonGenPredicate.cpp ------------------------------------------===//
+//===- HexagonGenPredicate.cpp --------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -81,8 +81,7 @@ namespace {
public:
static char ID;
- HexagonGenPredicate() : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr),
- MRI(nullptr) {
+ HexagonGenPredicate() : MachineFunctionPass(ID) {
initializeHexagonGenPredicatePass(*PassRegistry::getPassRegistry());
}
@@ -99,13 +98,13 @@ namespace {
bool runOnMachineFunction(MachineFunction &MF) override;
private:
- typedef SetVector<MachineInstr*> VectOfInst;
- typedef std::set<Register> SetOfReg;
- typedef std::map<Register,Register> RegToRegMap;
-
- const HexagonInstrInfo *TII;
- const HexagonRegisterInfo *TRI;
- MachineRegisterInfo *MRI;
+ using VectOfInst = SetVector<MachineInstr *>;
+ using SetOfReg = std::set<Register>;
+ using RegToRegMap = std::map<Register, Register>;
+
+ const HexagonInstrInfo *TII = nullptr;
+ const HexagonRegisterInfo *TRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
SetOfReg PredGPRs;
VectOfInst PUsers;
RegToRegMap G2P;
@@ -122,10 +121,10 @@ namespace {
bool eliminatePredCopies(MachineFunction &MF);
};
- char HexagonGenPredicate::ID = 0;
-
} // end anonymous namespace
+char HexagonGenPredicate::ID = 0;
+
INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
"Hexagon generate predicate operations", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
@@ -225,7 +224,8 @@ void HexagonGenPredicate::collectPredica
void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
DEBUG(dbgs() << __func__ << ": "
<< PrintReg(Reg.R, TRI, Reg.S) << "\n");
- typedef MachineRegisterInfo::use_iterator use_iterator;
+ using use_iterator = MachineRegisterInfo::use_iterator;
+
use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
if (I == E) {
DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n');
@@ -512,7 +512,8 @@ bool HexagonGenPredicate::runOnMachineFu
Again = false;
VectOfInst Processed, Copy;
- typedef VectOfInst::iterator iterator;
+ using iterator = VectOfInst::iterator;
+
Copy = PUsers;
for (iterator I = Copy.begin(), E = Copy.end(); I != E; ++I) {
MachineInstr *MI = *I;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===-- HexagonHardwareLoops.cpp - Identify and generate hardware loops ---===//
+//===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===//
//
// The LLVM Compiler Infrastructure
//
@@ -27,6 +27,8 @@
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
@@ -55,6 +57,7 @@
#include <iterator>
#include <map>
#include <set>
+#include <string>
#include <utility>
#include <vector>
@@ -123,7 +126,7 @@ namespace {
}
private:
- typedef std::map<unsigned, MachineInstr *> LoopFeederMap;
+ using LoopFeederMap = std::map<unsigned, MachineInstr *>;
/// Kinds of comparisons in the compare instructions.
struct Comparison {
@@ -344,10 +347,12 @@ namespace {
assert(isReg() && "Wrong CountValue accessor");
return Contents.R.Reg;
}
+
unsigned getSubReg() const {
assert(isReg() && "Wrong CountValue accessor");
return Contents.R.Sub;
}
+
unsigned getImm() const {
assert(isImm() && "Wrong CountValue accessor");
return Contents.ImmVal;
@@ -410,17 +415,18 @@ bool HexagonHardwareLoops::findInduction
// This pair represents an induction register together with an immediate
// value that will be added to it in each loop iteration.
- typedef std::pair<unsigned,int64_t> RegisterBump;
+ using RegisterBump = std::pair<unsigned, int64_t>;
// Mapping: R.next -> (R, bump), where R, R.next and bump are derived
// from an induction operation
// R.next = R + bump
// where bump is an immediate value.
- typedef std::map<unsigned,RegisterBump> InductionMap;
+ using InductionMap = std::map<unsigned, RegisterBump>;
InductionMap IndMap;
- typedef MachineBasicBlock::instr_iterator instr_iterator;
+ using instr_iterator = MachineBasicBlock::instr_iterator;
+
for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
I != E && I->isPHI(); ++I) {
MachineInstr *Phi = &*I;
@@ -970,6 +976,7 @@ bool HexagonHardwareLoops::isInvalidLoop
// Check if the instruction defines a hardware loop register.
using namespace Hexagon;
+
static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
static const unsigned Regs1[] = { LC1, SA1 };
auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
@@ -1017,7 +1024,7 @@ bool HexagonHardwareLoops::isDead(const
if (MRI->use_nodbg_empty(Reg))
continue;
- typedef MachineRegisterInfo::use_nodbg_iterator use_nodbg_iterator;
+ using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator;
// This instruction has users, but if the only user is the phi node for the
// parent block, and the only use of that phi node is this instruction, then
@@ -1300,7 +1307,8 @@ bool HexagonHardwareLoops::orderBumpComp
if (CmpI->getParent() != BB)
return false;
- typedef MachineBasicBlock::instr_iterator instr_iterator;
+ using instr_iterator = MachineBasicBlock::instr_iterator;
+
// Check if things are in order to begin with.
for (instr_iterator I(BumpI), E = BB->instr_end(); I != E; ++I)
if (&*I == CmpI)
@@ -1493,14 +1501,13 @@ bool HexagonHardwareLoops::checkForImmed
case Hexagon::A2_tfrsi:
case Hexagon::A2_tfrpi:
case Hexagon::CONST32:
- case Hexagon::CONST64: {
+ case Hexagon::CONST64:
// Call recursively to avoid an extra check whether operand(1) is
// indeed an immediate (it could be a global address, for example),
// plus we can handle COPY at the same time.
if (!checkForImmediate(DI->getOperand(1), TV))
return false;
break;
- }
case Hexagon::A2_combineii:
case Hexagon::A4_combineir:
case Hexagon::A4_combineii:
@@ -1589,9 +1596,9 @@ bool HexagonHardwareLoops::fixupInductio
// These data structures follow the same concept as the corresponding
// ones in findInductionRegister (where some comments are).
- typedef std::pair<unsigned,int64_t> RegisterBump;
- typedef std::pair<unsigned,RegisterBump> RegisterInduction;
- typedef std::set<RegisterInduction> RegisterInductionSet;
+ using RegisterBump = std::pair<unsigned, int64_t>;
+ using RegisterInduction = std::pair<unsigned, RegisterBump>;
+ using RegisterInductionSet = std::set<RegisterInduction>;
// Register candidates for induction variables, with their associated bumps.
RegisterInductionSet IndRegs;
@@ -1599,7 +1606,8 @@ bool HexagonHardwareLoops::fixupInductio
// Look for induction patterns:
// vreg1 = PHI ..., [ latch, vreg2 ]
// vreg2 = ADD vreg1, imm
- typedef MachineBasicBlock::instr_iterator instr_iterator;
+ using instr_iterator = MachineBasicBlock::instr_iterator;
+
for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
I != E && I->isPHI(); ++I) {
MachineInstr *Phi = &*I;
@@ -1834,18 +1842,19 @@ MachineBasicBlock *HexagonHardwareLoops:
DebugLoc DL;
#ifndef NDEBUG
- if ((PHFn != "") && (PHFn != MF->getName()))
+ if ((!PHFn.empty()) && (PHFn != MF->getName()))
return nullptr;
#endif
if (!Latch || !ExitingBlock || Header->hasAddressTaken())
return nullptr;
- typedef MachineBasicBlock::instr_iterator instr_iterator;
+ using instr_iterator = MachineBasicBlock::instr_iterator;
// Verify that all existing predecessors have analyzable branches
// (or no branches at all).
- typedef std::vector<MachineBasicBlock*> MBBVector;
+ using MBBVector = std::vector<MachineBasicBlock *>;
+
MBBVector Preds(Header->pred_begin(), Header->pred_end());
SmallVector<MachineOperand,2> Tmp1;
MachineBasicBlock *TB = nullptr, *FB = nullptr;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonLoopIdiomRecognition.cpp ----------------------------------===//
+//===- HexagonLoopIdiomRecognition.cpp ------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -9,28 +9,66 @@
#define DEBUG_TYPE "hexagon-lir"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/InstructionSimplify.h"
+#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/LoopPass.h"
+#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionExpander.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Dominators.h"
+#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InstrTypes.h"
+#include "llvm/IR/Instruction.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/User.h"
+#include "llvm/IR/Value.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/Local.h"
-
#include <algorithm>
#include <array>
+#include <cassert>
+#include <cstdint>
+#include <cstdlib>
+#include <deque>
+#include <functional>
+#include <iterator>
+#include <map>
+#include <set>
+#include <utility>
+#include <vector>
using namespace llvm;
@@ -67,17 +105,22 @@ static const char *HexagonVolatileMemcpy
namespace llvm {
+
void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
Pass *createHexagonLoopIdiomPass();
-}
+
+} // end namespace llvm
namespace {
+
class HexagonLoopIdiomRecognize : public LoopPass {
public:
static char ID;
+
explicit HexagonLoopIdiomRecognize() : LoopPass(ID) {
initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry());
}
+
StringRef getPassName() const override {
return "Recognize Hexagon-specific loop idioms";
}
@@ -116,26 +159,9 @@ namespace {
ScalarEvolution *SE;
bool HasMemcpy, HasMemmove;
};
-}
-
-char HexagonLoopIdiomRecognize::ID = 0;
-INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
- "Recognize Hexagon-specific loop idioms", false, false)
-INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LoopSimplify)
-INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
- "Recognize Hexagon-specific loop idioms", false, false)
-
-
-namespace {
struct Simplifier {
- typedef std::function<Value* (Instruction*, LLVMContext&)> Rule;
+ using Rule = std::function<Value * (Instruction *, LLVMContext &)>;
void addRule(const Rule &R) { Rules.push_back(R); }
@@ -147,10 +173,12 @@ namespace {
// Do not push back duplicates.
if (!S.count(V)) { Q.push_back(V); S.insert(V); }
}
+
Value *pop_front_val() {
Value *V = Q.front(); Q.pop_front(); S.erase(V);
return V;
}
+
bool empty() const { return Q.empty(); }
private:
@@ -158,12 +186,13 @@ namespace {
std::set<Value*> S;
};
- typedef std::set<Value*> ValueSetType;
+ using ValueSetType = std::set<Value *>;
+
std::vector<Rule> Rules;
public:
struct Context {
- typedef DenseMap<Value*,Value*> ValueMapType;
+ using ValueMapType = DenseMap<Value *, Value *>;
Value *Root;
ValueSetType Used; // The set of all cloned values used by Root.
@@ -174,12 +203,15 @@ namespace {
: Ctx(Exp->getParent()->getParent()->getContext()) {
initialize(Exp);
}
+
~Context() { cleanup(); }
- void print(raw_ostream &OS, const Value *V) const;
+ void print(raw_ostream &OS, const Value *V) const;
Value *materialize(BasicBlock *B, BasicBlock::iterator At);
private:
+ friend struct Simplifier;
+
void initialize(Instruction *Exp);
void cleanup();
@@ -193,8 +225,6 @@ namespace {
Value *subst(Value *Tree, Value *OldV, Value *NewV);
void replace(Value *OldV, Value *NewV);
void link(Instruction *I, BasicBlock *B, BasicBlock::iterator At);
-
- friend struct Simplifier;
};
Value *simplify(Context &C);
@@ -202,6 +232,7 @@ namespace {
struct PE {
PE(const Simplifier::Context &c, Value *v = nullptr) : C(c), V(v) {}
+
const Simplifier::Context &C;
const Value *V;
};
@@ -211,8 +242,22 @@ namespace {
P.C.print(OS, P.V ? P.V : P.C.Root);
return OS;
}
-}
+} // end anonymous namespace
+
+char HexagonLoopIdiomRecognize::ID = 0;
+
+INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
+ "Recognize Hexagon-specific loop idioms", false, false)
+INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(LoopSimplify)
+INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_END(HexagonLoopIdiomRecognize, "hexagon-loop-idiom",
+ "Recognize Hexagon-specific loop idioms", false, false)
template <typename FuncT>
void Simplifier::Context::traverse(Value *V, FuncT F) {
@@ -230,7 +275,6 @@ void Simplifier::Context::traverse(Value
}
}
-
void Simplifier::Context::print(raw_ostream &OS, const Value *V) const {
const auto *U = dyn_cast<const Instruction>(V);
if (!U) {
@@ -257,7 +301,6 @@ void Simplifier::Context::print(raw_ostr
OS << ')';
}
-
void Simplifier::Context::initialize(Instruction *Exp) {
// Perform a deep clone of the expression, set Root to the root
// of the clone, and build a map from the cloned values to the
@@ -297,7 +340,6 @@ void Simplifier::Context::initialize(Ins
use(Root);
}
-
void Simplifier::Context::record(Value *V) {
auto Record = [this](Instruction *U) -> bool {
Clones.insert(U);
@@ -306,7 +348,6 @@ void Simplifier::Context::record(Value *
traverse(V, Record);
}
-
void Simplifier::Context::use(Value *V) {
auto Use = [this](Instruction *U) -> bool {
Used.insert(U);
@@ -315,7 +356,6 @@ void Simplifier::Context::use(Value *V)
traverse(V, Use);
}
-
void Simplifier::Context::unuse(Value *V) {
if (!isa<Instruction>(V) || cast<Instruction>(V)->getParent() != nullptr)
return;
@@ -329,7 +369,6 @@ void Simplifier::Context::unuse(Value *V
traverse(V, Unuse);
}
-
Value *Simplifier::Context::subst(Value *Tree, Value *OldV, Value *NewV) {
if (Tree == OldV)
return NewV;
@@ -356,7 +395,6 @@ Value *Simplifier::Context::subst(Value
return Tree;
}
-
void Simplifier::Context::replace(Value *OldV, Value *NewV) {
if (Root == OldV) {
Root = NewV;
@@ -391,7 +429,6 @@ void Simplifier::Context::replace(Value
use(Root);
}
-
void Simplifier::Context::cleanup() {
for (Value *V : Clones) {
Instruction *U = cast<Instruction>(V);
@@ -406,7 +443,6 @@ void Simplifier::Context::cleanup() {
}
}
-
bool Simplifier::Context::equal(const Instruction *I,
const Instruction *J) const {
if (I == J)
@@ -431,7 +467,6 @@ bool Simplifier::Context::equal(const In
return true;
}
-
Value *Simplifier::Context::find(Value *Tree, Value *Sub) const {
Instruction *SubI = dyn_cast<Instruction>(Sub);
WorkListType Q;
@@ -453,7 +488,6 @@ Value *Simplifier::Context::find(Value *
return nullptr;
}
-
void Simplifier::Context::link(Instruction *I, BasicBlock *B,
BasicBlock::iterator At) {
if (I->getParent())
@@ -467,7 +501,6 @@ void Simplifier::Context::link(Instructi
B->getInstList().insert(At, I);
}
-
Value *Simplifier::Context::materialize(BasicBlock *B,
BasicBlock::iterator At) {
if (Instruction *RootI = dyn_cast<Instruction>(Root))
@@ -475,7 +508,6 @@ Value *Simplifier::Context::materialize(
return Root;
}
-
Value *Simplifier::simplify(Context &C) {
WorkListType Q;
Q.push_back(C.Root);
@@ -507,7 +539,6 @@ Value *Simplifier::simplify(Context &C)
return Count < Limit ? C.Root : nullptr;
}
-
//===----------------------------------------------------------------------===//
//
// Implementation of PolynomialMultiplyRecognize
@@ -515,6 +546,7 @@ Value *Simplifier::simplify(Context &C)
//===----------------------------------------------------------------------===//
namespace {
+
class PolynomialMultiplyRecognize {
public:
explicit PolynomialMultiplyRecognize(Loop *loop, const DataLayout &dl,
@@ -523,13 +555,15 @@ namespace {
: CurLoop(loop), DL(dl), DT(dt), TLI(tli), SE(se) {}
bool recognize();
+
private:
- typedef SetVector<Value*> ValueSeq;
+ using ValueSeq = SetVector<Value *>;
IntegerType *getPmpyType() const {
LLVMContext &Ctx = CurLoop->getHeader()->getParent()->getContext();
return IntegerType::get(Ctx, 32);
}
+
bool isPromotableTo(Value *V, IntegerType *Ty);
void promoteTo(Instruction *In, IntegerType *DestTy, BasicBlock *LoopB);
bool promoteTypes(BasicBlock *LoopB, BasicBlock *ExitB);
@@ -548,12 +582,17 @@ namespace {
void cleanupLoopBody(BasicBlock *LoopB);
struct ParsedValues {
- ParsedValues() : M(nullptr), P(nullptr), Q(nullptr), R(nullptr),
- X(nullptr), Res(nullptr), IterCount(0), Left(false), Inv(false) {}
- Value *M, *P, *Q, *R, *X;
- Instruction *Res;
- unsigned IterCount;
- bool Left, Inv;
+ ParsedValues() = default;
+
+ Value *M = nullptr;
+ Value *P = nullptr;
+ Value *Q = nullptr;
+ Value *R = nullptr;
+ Value *X = nullptr;
+ Instruction *Res = nullptr;
+ unsigned IterCount = 0;
+ bool Left = false;
+ bool Inv = false;
};
bool matchLeftShift(SelectInst *SelI, Value *CIV, ParsedValues &PV);
@@ -572,8 +611,8 @@ namespace {
const TargetLibraryInfo &TLI;
ScalarEvolution &SE;
};
-}
+} // end anonymous namespace
Value *PolynomialMultiplyRecognize::getCountIV(BasicBlock *BB) {
pred_iterator PI = pred_begin(BB), PE = pred_end(BB);
@@ -607,7 +646,6 @@ Value *PolynomialMultiplyRecognize::getC
return nullptr;
}
-
static void replaceAllUsesOfWithIn(Value *I, Value *J, BasicBlock *BB) {
for (auto UI = I->user_begin(), UE = I->user_end(); UI != UE;) {
Use &TheUse = UI.getUse();
@@ -618,7 +656,6 @@ static void replaceAllUsesOfWithIn(Value
}
}
-
bool PolynomialMultiplyRecognize::matchLeftShift(SelectInst *SelI,
Value *CIV, ParsedValues &PV) {
// Match the following:
@@ -734,7 +771,6 @@ bool PolynomialMultiplyRecognize::matchL
return true;
}
-
bool PolynomialMultiplyRecognize::matchRightShift(SelectInst *SelI,
ParsedValues &PV) {
// Match the following:
@@ -810,11 +846,11 @@ bool PolynomialMultiplyRecognize::matchR
return true;
}
-
bool PolynomialMultiplyRecognize::scanSelect(SelectInst *SelI,
BasicBlock *LoopB, BasicBlock *PrehB, Value *CIV, ParsedValues &PV,
bool PreScan) {
using namespace PatternMatch;
+
// The basic pattern for R = P.Q is:
// for i = 0..31
// R = phi (0, R')
@@ -917,7 +953,6 @@ bool PolynomialMultiplyRecognize::scanSe
return false;
}
-
bool PolynomialMultiplyRecognize::isPromotableTo(Value *Val,
IntegerType *DestTy) {
IntegerType *T = dyn_cast<IntegerType>(Val->getType());
@@ -955,7 +990,6 @@ bool PolynomialMultiplyRecognize::isProm
return false;
}
-
void PolynomialMultiplyRecognize::promoteTo(Instruction *In,
IntegerType *DestTy, BasicBlock *LoopB) {
// Leave boolean values alone.
@@ -997,7 +1031,6 @@ void PolynomialMultiplyRecognize::promot
}
}
-
bool PolynomialMultiplyRecognize::promoteTypes(BasicBlock *LoopB,
BasicBlock *ExitB) {
assert(LoopB);
@@ -1061,7 +1094,6 @@ bool PolynomialMultiplyRecognize::promot
return true;
}
-
bool PolynomialMultiplyRecognize::findCycle(Value *Out, Value *In,
ValueSeq &Cycle) {
// Out = ..., In, ...
@@ -1094,7 +1126,6 @@ bool PolynomialMultiplyRecognize::findCy
return !Cycle.empty();
}
-
void PolynomialMultiplyRecognize::classifyCycle(Instruction *DivI,
ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) {
// All the values in the cycle that are between the phi node and the
@@ -1131,7 +1162,6 @@ void PolynomialMultiplyRecognize::classi
First.insert(Cycle[I]);
}
-
bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI,
ValueSeq &Early, ValueSeq &Late) {
// Select is an exception, since the condition value does not have to be
@@ -1184,7 +1214,6 @@ bool PolynomialMultiplyRecognize::classi
return true;
}
-
bool PolynomialMultiplyRecognize::commutesWithShift(Instruction *I) {
switch (I->getOpcode()) {
case Instruction::And:
@@ -1202,7 +1231,6 @@ bool PolynomialMultiplyRecognize::commut
return true;
}
-
bool PolynomialMultiplyRecognize::highBitsAreZero(Value *V,
unsigned IterCount) {
auto *T = dyn_cast<IntegerType>(V->getType());
@@ -1214,7 +1242,6 @@ bool PolynomialMultiplyRecognize::highBi
return Known.countMinLeadingZeros() >= IterCount;
}
-
bool PolynomialMultiplyRecognize::keepsHighBitsZero(Value *V,
unsigned IterCount) {
// Assume that all inputs to the value have the high bits zero.
@@ -1239,7 +1266,6 @@ bool PolynomialMultiplyRecognize::keepsH
return false;
}
-
bool PolynomialMultiplyRecognize::isOperandShifted(Instruction *I, Value *Op) {
unsigned Opc = I->getOpcode();
if (Opc == Instruction::Shl || Opc == Instruction::LShr)
@@ -1247,7 +1273,6 @@ bool PolynomialMultiplyRecognize::isOper
return true;
}
-
bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB,
BasicBlock *ExitB, unsigned IterCount) {
Value *CIV = getCountIV(LoopB);
@@ -1263,6 +1288,7 @@ bool PolynomialMultiplyRecognize::conver
// Find all value cycles that contain logical right shifts by 1.
for (Instruction &I : *LoopB) {
using namespace PatternMatch;
+
Value *V = nullptr;
if (!match(&I, m_LShr(m_Value(V), m_One())))
continue;
@@ -1303,7 +1329,7 @@ bool PolynomialMultiplyRecognize::conver
}
}
- if (Users.size() == 0)
+ if (Users.empty())
return false;
// Verify that high bits remain zero.
@@ -1331,7 +1357,9 @@ bool PolynomialMultiplyRecognize::conver
// Finally, the work can be done. Unshift each user.
IRBuilder<> IRB(LoopB);
std::map<Value*,Value*> ShiftMap;
- typedef std::map<std::pair<Value*,Type*>,Value*> CastMapType;
+
+ using CastMapType = std::map<std::pair<Value *, Type *>, Value *>;
+
CastMapType CastMap;
auto upcast = [] (CastMapType &CM, IRBuilder<> &IRB, Value *V,
@@ -1345,9 +1373,11 @@ bool PolynomialMultiplyRecognize::conver
};
for (auto I = LoopB->begin(), E = LoopB->end(); I != E; ++I) {
+ using namespace PatternMatch;
+
if (isa<PHINode>(I) || !Users.count(&*I))
continue;
- using namespace PatternMatch;
+
// Match lshr x, 1.
Value *V = nullptr;
if (match(&*I, m_LShr(m_Value(V), m_One()))) {
@@ -1419,7 +1449,6 @@ bool PolynomialMultiplyRecognize::conver
return true;
}
-
void PolynomialMultiplyRecognize::cleanupLoopBody(BasicBlock *LoopB) {
for (auto &I : *LoopB)
if (Value *SV = SimplifyInstruction(&I, {DL, &TLI, &DT}))
@@ -1431,7 +1460,6 @@ void PolynomialMultiplyRecognize::cleanu
}
}
-
unsigned PolynomialMultiplyRecognize::getInverseMxN(unsigned QP) {
// Arrays of coefficients of Q and the inverse, C.
// Q[i] = coefficient at x^i.
@@ -1475,7 +1503,6 @@ unsigned PolynomialMultiplyRecognize::ge
return QV;
}
-
Value *PolynomialMultiplyRecognize::generate(BasicBlock::iterator At,
ParsedValues &PV) {
IRBuilder<> B(&*At);
@@ -1517,7 +1544,6 @@ Value *PolynomialMultiplyRecognize::gene
return R;
}
-
void PolynomialMultiplyRecognize::setupSimplifier() {
Simp.addRule(
// Sink zext past bitwise operations.
@@ -1670,7 +1696,6 @@ void PolynomialMultiplyRecognize::setupS
});
}
-
bool PolynomialMultiplyRecognize::recognize() {
DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n"
<< *CurLoop << '\n');
@@ -1789,7 +1814,6 @@ bool PolynomialMultiplyRecognize::recogn
return true;
}
-
unsigned HexagonLoopIdiomRecognize::getStoreSizeInBytes(StoreInst *SI) {
uint64_t SizeInBits = DL->getTypeSizeInBits(SI->getValueOperand()->getType());
assert(((SizeInBits & 7) || (SizeInBits >> 32) == 0) &&
@@ -1797,14 +1821,12 @@ unsigned HexagonLoopIdiomRecognize::getS
return (unsigned)SizeInBits >> 3;
}
-
int HexagonLoopIdiomRecognize::getSCEVStride(const SCEVAddRecExpr *S) {
if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(S->getOperand(1)))
return SC->getAPInt().getSExtValue();
return 0;
}
-
bool HexagonLoopIdiomRecognize::isLegalStore(Loop *CurLoop, StoreInst *SI) {
// Allow volatile stores if HexagonVolatileMemcpy is enabled.
if (!(SI->isVolatile() && HexagonVolatileMemcpy) && !SI->isSimple())
@@ -1855,7 +1877,6 @@ bool HexagonLoopIdiomRecognize::isLegalS
return true;
}
-
/// mayLoopAccessLocation - Return true if the specified loop might access the
/// specified pointer location, which is a loop-strided access. The 'Access'
/// argument specifies what the verboten forms of access are (read or write).
@@ -1888,7 +1909,6 @@ mayLoopAccessLocation(Value *Ptr, ModRef
return false;
}
-
void HexagonLoopIdiomRecognize::collectStores(Loop *CurLoop, BasicBlock *BB,
SmallVectorImpl<StoreInst*> &Stores) {
Stores.clear();
@@ -1898,7 +1918,6 @@ void HexagonLoopIdiomRecognize::collectS
Stores.push_back(SI);
}
-
bool HexagonLoopIdiomRecognize::processCopyingStore(Loop *CurLoop,
StoreInst *SI, const SCEV *BECount) {
assert((SI->isSimple() || (SI->isVolatile() && HexagonVolatileMemcpy)) &&
@@ -1998,7 +2017,7 @@ CleanupAndExit:
if (DisableMemmoveIdiom || !HasMemmove)
goto CleanupAndExit;
- bool IsNested = CurLoop->getParentLoop() != 0;
+ bool IsNested = CurLoop->getParentLoop() != nullptr;
if (IsNested && OnlyNonNestedMemmove)
goto CleanupAndExit;
}
@@ -2191,7 +2210,6 @@ CleanupAndExit:
return true;
}
-
// \brief Check if the instructions in Insts, together with their dependencies
// cover the loop in the sense that the loop could be safely eliminated once
// the instructions in Insts are removed.
@@ -2270,7 +2288,6 @@ bool HexagonLoopIdiomRecognize::runOnLoo
return MadeChange;
}
-
bool HexagonLoopIdiomRecognize::runOnCountableLoop(Loop *L) {
PolynomialMultiplyRecognize PMR(L, *DL, *DT, *TLI, *SE);
if (PMR.recognize())
@@ -2300,7 +2317,6 @@ bool HexagonLoopIdiomRecognize::runOnCou
return Changed;
}
-
bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) {
const Module &M = *L->getHeader()->getParent()->getParent();
if (Triple(M.getTargetTriple()).getArch() != Triple::hexagon)
@@ -2334,8 +2350,6 @@ bool HexagonLoopIdiomRecognize::runOnLoo
return false;
}
-
Pass *llvm::createHexagonLoopIdiomPass() {
return new HexagonLoopIdiomRecognize();
}
-
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonOptAddrMode.cpp -------------------------------------------===//
+//===- HexagonOptAddrMode.cpp ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -15,6 +15,8 @@
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "RDFGraph.h"
#include "RDFLiveness.h"
+#include "RDFRegisters.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -31,21 +33,24 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#define DEBUG_TYPE "opt-addr-mode"
+using namespace llvm;
+using namespace rdf;
+
static cl::opt<int> CodeGrowthLimit("hexagon-amode-growth-limit",
cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode "
"optimization"));
-using namespace llvm;
-using namespace rdf;
-
namespace llvm {
+
FunctionPass *createHexagonOptAddrMode();
void initializeHexagonOptAddrModePass(PassRegistry&);
+
} // end namespace llvm
namespace {
@@ -54,9 +59,7 @@ class HexagonOptAddrMode : public Machin
public:
static char ID;
- HexagonOptAddrMode()
- : MachineFunctionPass(ID), HII(nullptr), MDT(nullptr), DFG(nullptr),
- LV(nullptr) {}
+ HexagonOptAddrMode() : MachineFunctionPass(ID) {}
StringRef getPassName() const override {
return "Optimize addressing mode of load/store";
@@ -72,13 +75,14 @@ public:
bool runOnMachineFunction(MachineFunction &MF) override;
private:
- typedef DenseSet<MachineInstr *> MISetType;
- typedef DenseMap<MachineInstr *, bool> InstrEvalMap;
- const HexagonInstrInfo *HII;
- MachineDominatorTree *MDT;
- DataFlowGraph *DFG;
+ using MISetType = DenseSet<MachineInstr *>;
+ using InstrEvalMap = DenseMap<MachineInstr *, bool>;
+
+ const HexagonInstrInfo *HII = nullptr;
+ MachineDominatorTree *MDT = nullptr;
+ DataFlowGraph *DFG = nullptr;
DataFlowGraph::DefStackMap DefM;
- Liveness *LV;
+ Liveness *LV = nullptr;
MISetType Deleted;
bool processBlock(NodeAddr<BlockNode *> BA);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonRDFOpt.cpp ------------------------------------------------===//
+//===- HexagonRDFOpt.cpp --------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -9,49 +9,67 @@
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
+#include "MCTargetDesc/HexagonBaseInfo.h"
#include "RDFCopy.h"
#include "RDFDeadCode.h"
#include "RDFGraph.h"
#include "RDFLiveness.h"
+#include "RDFRegisters.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominanceFrontier.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <limits>
+#include <utility>
using namespace llvm;
using namespace rdf;
namespace llvm {
+
void initializeHexagonRDFOptPass(PassRegistry&);
FunctionPass *createHexagonRDFOpt();
-}
+
+} // end namespace llvm
+
+static unsigned RDFCount = 0;
+
+static cl::opt<unsigned> RDFLimit("rdf-limit",
+ cl::init(std::numeric_limits<unsigned>::max()));
+static cl::opt<bool> RDFDump("rdf-dump", cl::init(false));
namespace {
- unsigned RDFCount = 0;
- cl::opt<unsigned> RDFLimit("rdf-limit", cl::init(UINT_MAX));
- cl::opt<bool> RDFDump("rdf-dump", cl::init(false));
class HexagonRDFOpt : public MachineFunctionPass {
public:
HexagonRDFOpt() : MachineFunctionPass(ID) {
initializeHexagonRDFOptPass(*PassRegistry::getPassRegistry());
}
+
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachineDominanceFrontier>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
+
StringRef getPassName() const override {
return "Hexagon RDF optimizations";
}
+
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
@@ -66,32 +84,30 @@ namespace {
MachineRegisterInfo *MRI;
};
- char HexagonRDFOpt::ID = 0;
-}
-
-INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "rdfopt", "Hexagon RDF opt", false, false)
-INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
-INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
-INITIALIZE_PASS_END(HexagonRDFOpt, "rdfopt", "Hexagon RDF opt", false, false)
-
-
-namespace {
struct HexagonCP : public CopyPropagation {
HexagonCP(DataFlowGraph &G) : CopyPropagation(G) {}
+
bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) override;
};
-
struct HexagonDCE : public DeadCodeElimination {
HexagonDCE(DataFlowGraph &G, MachineRegisterInfo &MRI)
: DeadCodeElimination(G, MRI) {}
+
bool rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove);
void removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum);
bool run();
};
+
} // end anonymous namespace
+char HexagonRDFOpt::ID = 0;
+
+INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "rdfopt", "Hexagon RDF opt", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
+INITIALIZE_PASS_END(HexagonRDFOpt, "rdfopt", "Hexagon RDF opt", false, false)
bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
@@ -130,7 +146,6 @@ bool HexagonCP::interpretAsCopy(const Ma
return CopyPropagation::interpretAsCopy(MI, EM);
}
-
bool HexagonDCE::run() {
bool Collected = collect();
if (!Collected)
@@ -139,7 +154,8 @@ bool HexagonDCE::run() {
const SetVector<NodeId> &DeadNodes = getDeadNodes();
const SetVector<NodeId> &DeadInstrs = getDeadInstrs();
- typedef DenseMap<NodeId,NodeId> RefToInstrMap;
+ using RefToInstrMap = DenseMap<NodeId, NodeId>;
+
RefToInstrMap R2I;
SetVector<NodeId> PartlyDead;
DataFlowGraph &DFG = getDFG();
@@ -156,7 +172,6 @@ bool HexagonDCE::run() {
}
}
-
// Nodes to remove.
SetVector<NodeId> Remove = DeadInstrs;
@@ -171,7 +186,6 @@ bool HexagonDCE::run() {
return erase(Remove) || Changed;
}
-
void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
@@ -198,7 +212,6 @@ void HexagonDCE::removeOperand(NodeAddr<
}
}
-
bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
if (!getDFG().IsCode<NodeAttrs::Stmt>(IA))
return false;
@@ -246,7 +259,7 @@ bool HexagonDCE::rewrite(NodeAddr<InstrN
if (&DA.Addr->getOp() != &Op)
continue;
Defs = DFG.getRelatedRefs(IA, DA);
- if (!all_of(Defs, IsDead))
+ if (!llvm::all_of(Defs, IsDead))
return false;
break;
}
@@ -266,7 +279,6 @@ bool HexagonDCE::rewrite(NodeAddr<InstrN
return true;
}
-
bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
@@ -324,7 +336,6 @@ bool HexagonRDFOpt::runOnMachineFunction
return false;
}
-
FunctionPass *llvm::createHexagonRDFOpt() {
return new HexagonRDFOpt();
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp?rev=309469&r1=309468&r2=309469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp Fri Jul 28 17:56:56 2017
@@ -1,4 +1,4 @@
-//===--- HexagonSplitDouble.cpp -------------------------------------------===//
+//===- HexagonSplitDouble.cpp ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -51,19 +51,18 @@ namespace llvm {
} // end namespace llvm
-namespace {
+static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
+ cl::desc("Maximum number of split partitions"));
+static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
+ cl::desc("Do not split loads or stores"));
- static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
- cl::desc("Maximum number of split partitions"));
- static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
- cl::desc("Do not split loads or stores"));
+namespace {
class HexagonSplitDoubleRegs : public MachineFunctionPass {
public:
static char ID;
- HexagonSplitDoubleRegs() : MachineFunctionPass(ID), TRI(nullptr),
- TII(nullptr) {
+ HexagonSplitDoubleRegs() : MachineFunctionPass(ID) {
initializeHexagonSplitDoubleRegsPass(*PassRegistry::getPassRegistry());
}
@@ -82,16 +81,16 @@ namespace {
private:
static const TargetRegisterClass *const DoubleRC;
- const HexagonRegisterInfo *TRI;
- const HexagonInstrInfo *TII;
+ const HexagonRegisterInfo *TRI = nullptr;
+ const HexagonInstrInfo *TII = nullptr;
const MachineLoopInfo *MLI;
MachineRegisterInfo *MRI;
- typedef std::set<unsigned> USet;
- typedef std::map<unsigned,USet> UUSetMap;
- typedef std::pair<unsigned,unsigned> UUPair;
- typedef std::map<unsigned,UUPair> UUPairMap;
- typedef std::map<const MachineLoop*,USet> LoopRegMap;
+ using USet = std::set<unsigned>;
+ using UUSetMap = std::map<unsigned, USet>;
+ using UUPair = std::pair<unsigned, unsigned>;
+ using UUPairMap = std::map<unsigned, UUPair>;
+ using LoopRegMap = std::map<const MachineLoop *, USet>;
bool isInduction(unsigned Reg, LoopRegMap &IRM) const;
bool isVolatileInstr(const MachineInstr *MI) const;
@@ -117,17 +116,18 @@ namespace {
bool splitPartition(const USet &Part);
static int Counter;
+
static void dump_partition(raw_ostream&, const USet&,
const TargetRegisterInfo&);
};
- char HexagonSplitDoubleRegs::ID;
- int HexagonSplitDoubleRegs::Counter = 0;
- const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC
- = &Hexagon::DoubleRegsRegClass;
-
} // end anonymous namespace
+char HexagonSplitDoubleRegs::ID;
+int HexagonSplitDoubleRegs::Counter = 0;
+const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC =
+ &Hexagon::DoubleRegsRegClass;
+
INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
"Hexagon Split Double Registers", false, false)
@@ -217,8 +217,8 @@ bool HexagonSplitDoubleRegs::isFixedInst
}
void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
- typedef std::map<unsigned,unsigned> UUMap;
- typedef std::vector<unsigned> UVect;
+ using UUMap = std::map<unsigned, unsigned>;
+ using UVect = std::vector<unsigned>;
unsigned NumRegs = MRI->getNumVirtRegs();
BitVector DoubleRegs(NumRegs);
@@ -501,7 +501,8 @@ void HexagonSplitDoubleRegs::collectIndR
// Get the set of all double registers defined by phi nodes in the
// loop header.
- typedef std::vector<unsigned> UVect;
+ using UVect = std::vector<unsigned>;
+
UVect DP;
for (auto &MI : *HB) {
if (!MI.isPHI())
@@ -542,7 +543,8 @@ void HexagonSplitDoubleRegs::collectIndR
}
void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
- typedef std::vector<MachineLoop*> LoopVector;
+ using LoopVector = std::vector<MachineLoop *>;
+
LoopVector WorkQ;
for (auto I : *MLI)
@@ -1097,8 +1099,9 @@ void HexagonSplitDoubleRegs::collapseReg
}
bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
+ using MISet = std::set<MachineInstr *>;
+
const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
- typedef std::set<MachineInstr*> MISet;
bool Changed = false;
DEBUG(dbgs() << "Splitting partition: "; dump_partition(dbgs(), Part, *TRI);
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