[PATCH] D36036: Supported interleaved byte load-pattern of stride:4 VF(8, 16, 32).

[Farhana Aleen via Phabricator via llvm-commits]

Farhana created this revision.
Herald added a subscriber: mzolotukhin.

It looks like we can generalize this stride-4 interleaved pattern. The basic idea is to optimize them as a 128 bit vector so that we can use the vpshuf*. Once we have shuffled in all the interleaved elements we can just keep packing them until we build the vectors of desired elements. Similar way, stores can be handled.


https://reviews.llvm.org/D36036

Files:
  include/llvm/Analysis/VectorUtils.h
  lib/Analysis/VectorUtils.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InterleavedAccess.cpp
  test/CodeGen/X86/x86-interleaved-access.ll
  test/Transforms/InterleavedAccess/X86/interleaved-accesses-8bits.ll

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